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ec51e91eaa
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
28 lines
388 B
Plaintext
28 lines
388 B
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
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menu "Cache Support"
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config FDT_CACHE
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bool "FDT based cache drivers"
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depends on FDT
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select CACHE
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default n
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if FDT_CACHE
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config FDT_CACHE_SIFIVE_CCACHE
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bool "SiFive CCACHE FDT cache driver"
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default n
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config FDT_CACHE_SIFIVE_PL2
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bool "SiFive PL2 FDT cache driver"
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default n
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endif
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config CACHE
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bool "Cache support"
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default n
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endmenu
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