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https://github.com/riscv-software-src/opensbi.git
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beb0cd177f
On QEMU virt machine with large number of HARTs, some of the HARTs randomly fail to come out of wait_for_coldboot() due to one of the following race-conditions: 1) Failing HARTs are not able to acquire the coldboot_lock and update the coldboot_hartmask in wait_for_coldboot() before the coldboot HART acquires the coldboot_lock and sends IPI in wake_coldboot_harts() hence the failing HARTs never receive IPI from the coldboot HART. 2) Failing HARTs acquire the coldbood_lock and update the coldboot_hartmask before coldboot HART does sbi_scratch_init() so the sbi_hartmask_set_hartid() does not update the coldboot_hartmask on the failing HARTs hence they never receive IPI from the coldboot HART. To address this, use a simple busy-loop in wait_for_coldboot() for polling on coldboot_done flag. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
65 lines
1.4 KiB
C
65 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_BARRIER_H__
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#define __RISCV_BARRIER_H__
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/* clang-format off */
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#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
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#define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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#define RISCV_FENCE_I \
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__asm__ __volatile__ ("fence.i" : : : "memory")
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/* Read & Write Memory barrier */
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#define mb() RISCV_FENCE(iorw,iorw)
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/* Read Memory barrier */
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#define rmb() RISCV_FENCE(ir,ir)
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/* Write Memory barrier */
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#define wmb() RISCV_FENCE(ow,ow)
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/* SMP Read & Write Memory barrier */
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#define smp_mb() RISCV_FENCE(rw,rw)
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/* SMP Read Memory barrier */
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#define smp_rmb() RISCV_FENCE(r,r)
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/* SMP Write Memory barrier */
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#define smp_wmb() RISCV_FENCE(w,w)
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/* CPU relax for busy loop */
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#define cpu_relax() \
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do { \
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unsigned long __t; \
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__asm__ __volatile__ ("div %0, %0, zero" : "=r" (__t)); \
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} while (0)
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/* clang-format on */
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#define __smp_store_release(p, v) \
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do { \
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RISCV_FENCE(rw, w); \
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*(p) = (v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = *(p); \
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RISCV_FENCE(r, rw); \
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___p1; \
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})
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#endif
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