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b27ecec76b
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Andes Technology Corporation
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*/
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#ifndef __FDT_HSM_ANDES_ATCSMU_H__
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#define __FDT_HSM_ANDES_ATCSMU_H__
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#include <sbi/sbi_types.h>
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/* clang-format off */
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#define SCRATCH_PAD_OFFSET 0x40
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#define RESET_VEC_LO_OFFSET 0x50
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#define RESET_VEC_HI_OFFSET 0x60
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#define RESET_VEC_8CORE_OFFSET 0x1a0
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#define HARTn_RESET_VEC_LO(n) (RESET_VEC_LO_OFFSET + \
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((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + \
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((n) * 0x4))
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#define HARTn_RESET_VEC_HI(n) (RESET_VEC_HI_OFFSET + \
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((n) < 4 ? 0 : RESET_VEC_8CORE_OFFSET) + \
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((n) * 0x4))
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#define PCS0_CFG_OFFSET 0x80
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#define PCSm_CFG_OFFSET(i) ((i + 3) * 0x20 + PCS0_CFG_OFFSET)
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#define PCS_CFG_LIGHT_SLEEP BIT(2)
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#define PCS_CFG_DEEP_SLEEP BIT(3)
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#define PCS0_SCRATCH_OFFSET 0x84
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#define PCSm_SCRATCH_OFFSET(i) ((i + 3) * 0x20 + PCS0_SCRATCH_OFFSET)
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#define PCS0_WE_OFFSET 0x90
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#define PCSm_WE_OFFSET(i) ((i + 3) * 0x20 + PCS0_WE_OFFSET)
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#define PCS_WAKEUP_RTC_ALARM_MASK BIT(2)
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#define PCS_WAKEUP_UART2_MASK BIT(9)
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#define PCS_WAKEUP_MSIP_MASK BIT(29)
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#define PCS0_CTL_OFFSET 0x94
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#define PCSm_CTL_OFFSET(i) ((i + 3) * 0x20 + PCS0_CTL_OFFSET)
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#define LIGHT_SLEEP_CMD 0x3
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#define WAKEUP_CMD 0x8
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#define DEEP_SLEEP_CMD 0xb
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#define PCS0_STATUS_OFFSET 0x98
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#define PCSm_STATUS_OFFSET(i) ((i + 3) * 0x20 + PCS0_STATUS_OFFSET)
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#define PD_TYPE_MASK GENMASK(2, 0)
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#define PD_TYPE_SLEEP 2
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#define PD_STATUS_MASK GENMASK(7, 3)
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#define PD_STATUS_LIGHT_SLEEP 0
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#define PD_STATUS_DEEP_SLEEP 0x10
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/* clang-format on */
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void atcsmu_set_wakeup_events(u32 events, u32 hartid);
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bool atcsmu_support_sleep_mode(u32 sleep_type, u32 hartid);
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void atcsmu_set_command(u32 pcs_ctl, u32 hartid);
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int atcsmu_set_reset_vector(u64 wakeup_addr, u32 hartid);
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u32 atcsmu_get_sleep_type(u32 hartid);
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void atcsmu_write_scratch(u32 value);
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u32 atcsmu_read_scratch(void);
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bool atcsmu_pcs_is_sleep(u32 hartid, bool deep_sleep);
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#endif
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