mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 23:41:23 +01:00
dd8ef28b27
We get following compile error for FW_PAYLOAD with latest GCC binutils: fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte boundary, but only 14 present Further investigating, it turn-out to be a known issue with RISC-V GCC binutils. (Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298) As a work-around, we disable relaxation when including DTB and PAYLOAD binary in fw_payload.S. Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
116 lines
2.1 KiB
ArmAsm
116 lines
2.1 KiB
ArmAsm
/*
|
|
* SPDX-License-Identifier: BSD-2-Clause
|
|
*
|
|
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
|
*
|
|
* Authors:
|
|
* Anup Patel <anup.patel@wdc.com>
|
|
*/
|
|
|
|
#include "fw_base.S"
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_save_info
|
|
/*
|
|
* We can only use a0, a1, a2, a3, and a4 registers here.
|
|
* The a0, a1, and a2 registers will be same as passed by
|
|
* previous booting stage.
|
|
* Nothing to be returned here.
|
|
*/
|
|
fw_save_info:
|
|
ret
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_prev_arg1
|
|
/*
|
|
* We can only use a0, a1, and a2 registers here.
|
|
* The previous arg1 should be returned in 'a0'.
|
|
*/
|
|
fw_prev_arg1:
|
|
#ifdef FW_PAYLOAD_FDT_PATH
|
|
la a0, fdt_bin
|
|
#else
|
|
add a0, zero, zero
|
|
#endif
|
|
ret
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_next_arg1
|
|
/*
|
|
* We can only use a0, a1, and a2 registers here.
|
|
* The next arg1 should be returned in 'a0'.
|
|
*/
|
|
fw_next_arg1:
|
|
#ifdef FW_PAYLOAD_FDT_ADDR
|
|
li a0, FW_PAYLOAD_FDT_ADDR
|
|
#else
|
|
add a0, zero, zero
|
|
#endif
|
|
ret
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_next_addr
|
|
/*
|
|
* We can only use a0, a1, and a2 registers here.
|
|
* The next address should be returned in 'a0'.
|
|
*/
|
|
fw_next_addr:
|
|
la a0, payload_bin
|
|
ret
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_next_mode
|
|
/*
|
|
* We can only use a0, a1, and a2 registers here.
|
|
* The next address should be returned in 'a0'.
|
|
*/
|
|
fw_next_mode:
|
|
li a0, PRV_S
|
|
ret
|
|
|
|
.align 3
|
|
.section .entry, "ax", %progbits
|
|
.global fw_options
|
|
/*
|
|
* We can only use a0, a1, and a2 registers here.
|
|
* The 'a4' register will have default options.
|
|
* The next address should be returned in 'a0'.
|
|
*/
|
|
fw_options:
|
|
add a0, zero, zero
|
|
ret
|
|
|
|
/*
|
|
* We disable relaxation because use of ".align"
|
|
* and ".balign" can potentially generate compile
|
|
* errors with latest RISC-V GCC Binutils.
|
|
*/
|
|
.option push
|
|
.option norelax
|
|
|
|
#ifdef FW_PAYLOAD_FDT_PATH
|
|
.align 4
|
|
.section .text, "ax", %progbits
|
|
.globl fdt_bin
|
|
fdt_bin:
|
|
.incbin FW_PAYLOAD_FDT_PATH
|
|
#endif
|
|
|
|
.align 4
|
|
.section .payload, "ax", %progbits
|
|
.globl payload_bin
|
|
payload_bin:
|
|
#ifndef FW_PAYLOAD_PATH
|
|
wfi
|
|
j payload_bin
|
|
#else
|
|
.incbin FW_PAYLOAD_PATH
|
|
#endif
|
|
|
|
.option pop
|