mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 23:41:23 +01:00

Illegal CSR accesses from lower privilege modes are delegated to S-mode and do not necessarily indicate a bug. Supervisor software may want to emulate some CSRs, or may intentionally disable access to certain existing CSRs, and thus will expect traps when those CSRs are accessed. For example, Linux disables sstatus.VS by default in order to detect when userspace first accesses vector register state; this includes the CSRs defined by the V extesion. As a result, if the first vector instruction in a process is a CSR access, OpenSBI will log the illegal instruction exception, even though there is no unexpected or erroneous behavior occurring. Since the illegal instruction exception is delegated to S-mode, S-mode software should be responsible for reporting the exception, not OpenSBI. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>