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https://github.com/riscv-software-src/opensbi.git
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d36709fcaf
This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.
With this update, both regions will become M-mode only read/write
regions in the root domain.
Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
p/x $pmpcfg0
$1 = {0x1f9b9b9d9b1e00,
pmp0cfg = {0x0},
L--AAXWR
pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1)
pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff
pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff
pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff
pmp7cfg = {0x0 }}
The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
p/x $pmpcfg0
$1 = {0x1f181818181b,
L--AAXWR
pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1)
pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff
pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff
pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff
pmp6cfg = {0x0 }}
Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
108 lines
2.2 KiB
C
108 lines
2.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/timer/andes_plmt.h>
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struct plmt_data plmt;
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static u64 plmt_timer_value(void)
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{
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#if __riscv_xlen == 64
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return readq_relaxed(plmt.time_val);
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#else
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u32 lo, hi;
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do {
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hi = readl_relaxed((void *)plmt.time_val + 0x04);
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lo = readl_relaxed(plmt.time_val);
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} while (hi != readl_relaxed((void *)plmt.time_val + 0x04));
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return ((u64)hi << 32) | (u64)lo;
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#endif
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}
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static void plmt_timer_event_stop(void)
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{
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u32 target_hart = current_hartid();
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if (plmt.hart_count <= target_hart)
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ebreak();
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/* Clear PLMT Time Compare */
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#if __riscv_xlen == 64
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writeq_relaxed(-1ULL, &plmt.time_cmp[target_hart]);
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#else
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writel_relaxed(-1UL, &plmt.time_cmp[target_hart]);
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writel_relaxed(-1UL, (void *)(&plmt.time_cmp[target_hart]) + 0x04);
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#endif
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}
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static void plmt_timer_event_start(u64 next_event)
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{
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u32 target_hart = current_hartid();
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if (plmt.hart_count <= target_hart)
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ebreak();
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/* Program PLMT Time Compare */
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#if __riscv_xlen == 64
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writeq_relaxed(next_event, &plmt.time_cmp[target_hart]);
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#else
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u32 mask = -1UL;
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writel_relaxed(next_event & mask, &plmt.time_cmp[target_hart]);
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writel_relaxed(next_event >> 32,
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(void *)(&plmt.time_cmp[target_hart]) + 0x04);
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#endif
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}
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static struct sbi_timer_device plmt_timer = {
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.name = "andes_plmt",
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.timer_freq = DEFAULT_AE350_PLMT_FREQ,
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.timer_value = plmt_timer_value,
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.timer_event_start = plmt_timer_event_start,
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.timer_event_stop = plmt_timer_event_stop
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};
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int plmt_cold_timer_init(struct plmt_data *plmt)
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{
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int rc;
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/* Add PLMT region to the root domain */
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rc = sbi_domain_root_add_memrange(
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(unsigned long)plmt->time_val, plmt->size,
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PLMT_REGION_ALIGN,
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SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE);
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if (rc)
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return rc;
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plmt_timer.timer_freq = plmt->timer_freq;
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sbi_timer_set_device(&plmt_timer);
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return 0;
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}
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int plmt_warm_timer_init(void)
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{
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if (!plmt.time_val)
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return SBI_ENODEV;
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plmt_timer_event_stop();
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return 0;
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}
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