mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 15:31:22 +01:00
d36709fcaf
This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.
With this update, both regions will become M-mode only read/write
regions in the root domain.
Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
p/x $pmpcfg0
$1 = {0x1f9b9b9d9b1e00,
pmp0cfg = {0x0},
L--AAXWR
pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1)
pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff
pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff
pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff
pmp7cfg = {0x0 }}
The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
p/x $pmpcfg0
$1 = {0x1f181818181b,
L--AAXWR
pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1)
pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff
pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff
pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT)
pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW)
pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff
pmp6cfg = {0x0 }}
Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
/*
|
|
* SPDX-License-Identifier: BSD-2-Clause
|
|
*
|
|
* Copyright (c) 2022 Andes Technology Corporation
|
|
*
|
|
* Authors:
|
|
* Zong Li <zong@andestech.com>
|
|
* Nylon Chen <nylon7@andestech.com>
|
|
* Leo Yu-Chi Liang <ycliang@andestech.com>
|
|
* Yu Chien Peter Lin <peterlin@andestech.com>
|
|
*/
|
|
|
|
#include <sbi/riscv_asm.h>
|
|
#include <sbi/riscv_io.h>
|
|
#include <sbi/sbi_domain.h>
|
|
#include <sbi/sbi_ipi.h>
|
|
#include <sbi_utils/ipi/andes_plicsw.h>
|
|
|
|
struct plicsw_data plicsw;
|
|
|
|
static inline void plicsw_claim(void)
|
|
{
|
|
u32 hartid = current_hartid();
|
|
|
|
if (plicsw.hart_count <= hartid)
|
|
ebreak();
|
|
|
|
plicsw.source_id[hartid] =
|
|
readl((void *)plicsw.addr + PLICSW_CONTEXT_BASE +
|
|
PLICSW_CONTEXT_CLAIM + PLICSW_CONTEXT_STRIDE * hartid);
|
|
}
|
|
|
|
static inline void plicsw_complete(void)
|
|
{
|
|
u32 hartid = current_hartid();
|
|
u32 source = plicsw.source_id[hartid];
|
|
|
|
writel(source, (void *)plicsw.addr + PLICSW_CONTEXT_BASE +
|
|
PLICSW_CONTEXT_CLAIM +
|
|
PLICSW_CONTEXT_STRIDE * hartid);
|
|
}
|
|
|
|
static inline void plic_sw_pending(u32 target_hart)
|
|
{
|
|
/*
|
|
* The pending array registers are w1s type.
|
|
* IPI pending array mapping as following:
|
|
*
|
|
* Pending array start address: base + 0x1000
|
|
* ---------------------------------
|
|
* | hart3 | hart2 | hart1 | hart0 |
|
|
* ---------------------------------
|
|
* Each hartX can send IPI to another hart by setting the
|
|
* bitY to its own region (see the below).
|
|
*
|
|
* In each hartX region:
|
|
* <---------- PICSW_PENDING_STRIDE -------->
|
|
* | bit7 | ... | bit3 | bit2 | bit1 | bit0 |
|
|
* ------------------------------------------
|
|
* The bitY of hartX region indicates that hartX sends an
|
|
* IPI to hartY.
|
|
*/
|
|
u32 hartid = current_hartid();
|
|
u32 word_index = hartid / 4;
|
|
u32 per_hart_offset = PLICSW_PENDING_STRIDE * hartid;
|
|
u32 val = 1 << target_hart << per_hart_offset;
|
|
|
|
writel(val, (void *)plicsw.addr + PLICSW_PENDING_BASE + word_index * 4);
|
|
}
|
|
|
|
static void plicsw_ipi_send(u32 hart_index)
|
|
{
|
|
u32 target_hart = sbi_hartindex_to_hartid(hart_index);
|
|
|
|
if (plicsw.hart_count <= target_hart)
|
|
ebreak();
|
|
|
|
/* Set PLICSW IPI */
|
|
plic_sw_pending(target_hart);
|
|
}
|
|
|
|
static void plicsw_ipi_clear(u32 hart_index)
|
|
{
|
|
u32 target_hart = sbi_hartindex_to_hartid(hart_index);
|
|
|
|
if (plicsw.hart_count <= target_hart)
|
|
ebreak();
|
|
|
|
/* Clear PLICSW IPI */
|
|
plicsw_claim();
|
|
plicsw_complete();
|
|
}
|
|
|
|
static struct sbi_ipi_device plicsw_ipi = {
|
|
.name = "andes_plicsw",
|
|
.ipi_send = plicsw_ipi_send,
|
|
.ipi_clear = plicsw_ipi_clear
|
|
};
|
|
|
|
int plicsw_warm_ipi_init(void)
|
|
{
|
|
u32 hartid = current_hartid();
|
|
|
|
/* Clear PLICSW IPI */
|
|
plicsw_ipi_clear(hartid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
|
|
{
|
|
int rc;
|
|
|
|
/* Setup source priority */
|
|
uint32_t *priority = (void *)plicsw->addr + PLICSW_PRIORITY_BASE;
|
|
|
|
for (int i = 0; i < plicsw->hart_count; i++)
|
|
writel(1, &priority[i]);
|
|
|
|
/* Setup target enable */
|
|
uint32_t enable_mask = PLICSW_HART_MASK;
|
|
|
|
for (int i = 0; i < plicsw->hart_count; i++) {
|
|
uint32_t *enable = (void *)plicsw->addr + PLICSW_ENABLE_BASE +
|
|
PLICSW_ENABLE_STRIDE * i;
|
|
writel(enable_mask, enable);
|
|
writel(enable_mask, enable + 1);
|
|
enable_mask <<= 1;
|
|
}
|
|
|
|
/* Add PLICSW region to the root domain */
|
|
rc = sbi_domain_root_add_memrange(plicsw->addr, plicsw->size,
|
|
PLICSW_REGION_ALIGN,
|
|
SBI_DOMAIN_MEMREGION_MMIO |
|
|
SBI_DOMAIN_MEMREGION_M_READABLE |
|
|
SBI_DOMAIN_MEMREGION_M_WRITABLE);
|
|
if (rc)
|
|
return rc;
|
|
|
|
sbi_ipi_set_device(&plicsw_ipi);
|
|
|
|
return 0;
|
|
}
|