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https://github.com/riscv-software-src/opensbi.git
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d10c1f4acd
We extend SBI PMU implementation to allow custom PMU device operations which a platform can use for platform specific quirks. The custom PMU device operations added by this patch include: 1) Operations to allow a platform implement custom firmware events. These custom firmware events can be SBI vendor extension related events or platform specific per-HART events are not possible to count through HPM CSRs. 2) Operations to allow a platform implement custom way for enabling (or disabling) an overflow interrupt (e.g. T-Head C9xx). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#ifndef __SBI_PMU_H__
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#define __SBI_PMU_H__
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#include <sbi/sbi_types.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_ecall_interface.h>
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/* Event related macros */
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/* Maximum number of hardware events that can mapped by OpenSBI */
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#define SBI_PMU_HW_EVENT_MAX 256
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/* Counter related macros */
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#define SBI_PMU_FW_CTR_MAX 16
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#define SBI_PMU_HW_CTR_MAX 32
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#define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX)
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#define SBI_PMU_FIXED_CTR_MASK 0x07
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struct sbi_pmu_device {
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/** Name of the PMU platform device */
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char name[32];
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/**
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* Validate event code of custom firmware event
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* Note: SBI_PMU_FW_MAX <= event_idx_code
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*/
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int (*fw_event_validate_code)(uint32_t event_idx_code);
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/**
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* Match custom firmware counter with custom firmware event
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* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
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*/
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bool (*fw_counter_match_code)(uint32_t counter_index,
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uint32_t event_idx_code);
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/**
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* Read value of custom firmware counter
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* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
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*/
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uint64_t (*fw_counter_read_value)(uint32_t counter_index);
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/**
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* Start custom firmware counter
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* Note: SBI_PMU_FW_MAX <= event_idx_code
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* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
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*/
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int (*fw_counter_start)(uint32_t counter_index,
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uint32_t event_idx_code,
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uint64_t init_val, bool init_val_update);
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/**
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* Stop custom firmware counter
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* Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX
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*/
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int (*fw_counter_stop)(uint32_t counter_index);
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/**
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* Custom enable irq for hardware counter
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* Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
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*/
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void (*hw_counter_enable_irq)(uint32_t counter_index);
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/**
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* Custom disable irq for hardware counter
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* Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
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*/
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void (*hw_counter_disable_irq)(uint32_t counter_index);
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};
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/** Get the PMU platform device */
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const struct sbi_pmu_device *sbi_pmu_get_device(void);
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/** Set the PMU platform device */
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void sbi_pmu_set_device(const struct sbi_pmu_device *dev);
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/** Initialize PMU */
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int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot);
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/** Reset PMU during hart exit */
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void sbi_pmu_exit(struct sbi_scratch *scratch);
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/**
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* Add the hardware event to counter mapping information. This should be called
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* from the platform code to update the mapping table.
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* @param eidx_start Start of the event idx range for supported counters
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* @param eidx_end End of the event idx range for supported counters
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* @param cmap A bitmap representing counters supporting the event range
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* @return 0 on success, error otherwise.
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*/
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int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap);
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/**
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* Add the raw hardware event selector and supported counter information. This
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* should be called from the platform code to update the mapping table.
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* @param info a pointer to the hardware event info
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* @return 0 on success, error otherwise.
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*/
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int sbi_pmu_add_raw_event_counter_map(uint64_t select, uint64_t select_mask, u32 cmap);
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int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval);
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int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flag);
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int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flags, uint64_t ival);
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int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info);
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unsigned long sbi_pmu_num_ctr(void);
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int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask,
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unsigned long flags, unsigned long event_idx,
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uint64_t event_data);
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int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id);
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#endif
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