mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-07-02 22:02:01 +01:00
Junhui Liu
cc9b4ef8f3
PMU_AP_CORE2_IDLE_CFG and PMU_AP_CORE3_IDLE_CFG are not continuous with
PMU_AP_CORE0_IDLE_CFG and PMU_AP_CORE1_IDLE_CFG. They are at PMU AP
base + 0x160 and + 0x164, matching the vendor OpenSBI definitions. After
fixing these addresses, the intermediate cluster offset macros are
redundant now, so define the wakeup and idle registers directly as
PMU_AP_BASE offsets. This makes the actual register addresses easier to
inspect and compare against the vendor code.
C1_RVBADDR_HI_ADDR is also corrected according to the vendor OpenSBI
definition. This was tested by writing an invalid value to the corrected
address, which prevents cluster1 CPUs from coming online, while doing
the same with the old address does not affect SMP boot.
Fixes: 1f84ec2a ("platform: generic: spacemit: add K1")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20260623-k1-fix-addr-v1-1-3dbde8c03bd6@pigmoral.tech
Signed-off-by: Anup Patel <anup@brainfault.org>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
#ifndef __RISCV_SPACEMIT_K1_H__
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#define __RISCV_SPACEMIT_K1_H__
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#define CSR_MSETUP 0x7c0
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#define CSR_MHCR 0x7c1
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#define CSR_MRAOP 0x7c2
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#define CSR_MHINT 0x7c5
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#define CSR_ML2SETUP 0x7f0
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/* decache enable */
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#define MSETUP_DE BIT(0)
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/* icache enable */
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#define MSETUP_IE BIT(1)
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/* branch prediction enable */
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#define MSETUP_BPE BIT(4)
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/* prefetch functionality enable */
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#define MSETUP_PFE BIT(5)
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/* misaligned memory access enable */
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#define MSETUP_MME BIT(6)
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/* ECC enable */
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#define MSETUP_ECCE BIT(16)
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/* icache invalidation */
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#define MRAOP_ICACHE_INVALID GENMASK(1, 0)
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#define PMU_AP_BASE 0xd4282800
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#define PMU_AP_CORE0_WAKEUP (PMU_AP_BASE + 0x12c)
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#define PMU_AP_CORE1_WAKEUP (PMU_AP_BASE + 0x130)
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#define PMU_AP_CORE2_WAKEUP (PMU_AP_BASE + 0x134)
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#define PMU_AP_CORE3_WAKEUP (PMU_AP_BASE + 0x138)
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#define PMU_AP_CORE4_WAKEUP (PMU_AP_BASE + 0x324)
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#define PMU_AP_CORE5_WAKEUP (PMU_AP_BASE + 0x328)
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#define PMU_AP_CORE6_WAKEUP (PMU_AP_BASE + 0x32c)
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#define PMU_AP_CORE7_WAKEUP (PMU_AP_BASE + 0x330)
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#define PMU_AP_CORE0_IDLE_CFG (PMU_AP_BASE + 0x124)
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#define PMU_AP_CORE1_IDLE_CFG (PMU_AP_BASE + 0x128)
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#define PMU_AP_CORE2_IDLE_CFG (PMU_AP_BASE + 0x160)
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#define PMU_AP_CORE3_IDLE_CFG (PMU_AP_BASE + 0x164)
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#define PMU_AP_CORE4_IDLE_CFG (PMU_AP_BASE + 0x304)
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#define PMU_AP_CORE5_IDLE_CFG (PMU_AP_BASE + 0x308)
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#define PMU_AP_CORE6_IDLE_CFG (PMU_AP_BASE + 0x30c)
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#define PMU_AP_CORE7_IDLE_CFG (PMU_AP_BASE + 0x310)
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/* power down */
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#define PMU_AP_IDLE_PWRDWN BIT(0)
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/* sram power down */
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#define PMU_AP_IDLE_SRAM_PWRDWN BIT(1)
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/* enable wake up the memory controller */
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#define PMU_AP_IDLE_WAKE_MCE BIT(3)
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/* disable memory controller software req */
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#define PMU_AP_IDLE_MC_SW_REQ BIT(4)
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#define PMU_AP_IDLE_PWRDOWN_MASK (PMU_AP_IDLE_PWRDWN | PMU_AP_IDLE_SRAM_PWRDWN | \
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PMU_AP_IDLE_WAKE_MCE | PMU_AP_IDLE_MC_SW_REQ)
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/* cci */
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#define C0_RVBADDR_LO_ADDR 0xd4282db0
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#define C0_RVBADDR_HI_ADDR 0xd4282db4
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#define C1_RVBADDR_LO_ADDR 0xd4282eb0
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#define C1_RVBADDR_HI_ADDR 0xd4282eb4
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#define CCI_550_PLATFORM_CCI_ADDR 0xd8500000
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/* relative to cci base */
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#define CCI_550_STATUS 0x000c
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/* status register bits */
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#define CCI_550_STATUS_CHANGE_PENDING BIT(0)
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/* slave interface registers */
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#define CCI_550_SLAVE_IFACE0_OFFSET 0x1000
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#define CCI_550_SLAVE_IFACE_OFFSET(idx) (CCI_550_SLAVE_IFACE0_OFFSET + ((0x1000) * (idx)))
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/* relative to slave interface base */
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#define CCI_550_SNOOP_CTRL 0x0000
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/* snoop control register bits */
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#define CCI_550_SNOOP_CTRL_ENABLE_SNOOPS BIT(0)
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#define CCI_550_SNOOP_CTRL_ENABLE_DVMS BIT(1)
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/* clusters and CPU mapping */
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#define PLATFORM_MAX_CPUS 8
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define CPU_TO_CLUSTER(cpu) ((cpu) / PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLAT_CCI_CLUSTER0_IFACE_IX 0
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#define PLAT_CCI_CLUSTER1_IFACE_IX 1
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#endif
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