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https://github.com/riscv-software-src/opensbi.git
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c69c159bd0
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#ifndef __P8700_H__
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#define __P8700_H__
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#include <mips/board.h>
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/* PMA */
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#define CSR_MIPSPMACFG0 0x7e0
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#define CSR_MIPSPMACFG1 0x7e1
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#define CSR_MIPSPMACFG2 0x7e2
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#define CSR_MIPSPMACFG3 0x7e3
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#define CSR_MIPSPMACFG4 0x7e4
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#define CSR_MIPSPMACFG5 0x7e5
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#define CSR_MIPSPMACFG6 0x7e6
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#define CSR_MIPSPMACFG7 0x7e7
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#define CSR_MIPSPMACFG8 0x7e8
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#define CSR_MIPSPMACFG9 0x7e9
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#define CSR_MIPSPMACFG10 0x7ea
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#define CSR_MIPSPMACFG11 0x7eb
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#define CSR_MIPSPMACFG12 0x7ec
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#define CSR_MIPSPMACFG13 0x7ed
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#define CSR_MIPSPMACFG14 0x7ee
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#define CSR_MIPSPMACFG15 0x7ef
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/* MIPS CCA */
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#define CCA_CACHE_ENABLE 0
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#define CCA_CACHE_DISABLE 2
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#define PMA_SPECULATION (1 << 3)
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/* MIPS CSR */
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#define CSR_MIPSTVEC 0x7c0
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#define CSR_MIPSCONFIG0 0x7d0
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#define CSR_MIPSCONFIG1 0x7d1
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#define CSR_MIPSCONFIG2 0x7d2
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#define CSR_MIPSCONFIG3 0x7d3
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#define CSR_MIPSCONFIG4 0x7d4
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#define CSR_MIPSCONFIG5 0x7d5
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#define CSR_MIPSCONFIG6 0x7d6
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#define CSR_MIPSCONFIG7 0x7d7
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#define CSR_MIPSCONFIG8 0x7d8
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#define CSR_MIPSCONFIG9 0x7d9
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#define CSR_MIPSCONFIG10 0x7da
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#define CSR_MIPSCONFIG11 0x7db
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#define MIPSCONFIG5_MTW 4
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#define GEN_MASK(h, l) (((1ul << ((h) + 1 - (l))) - 1) << (l))
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#define EXT(val, mask) (((val) & (mask)) >> (__builtin_ffs(mask) - 1))
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/*
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* We allocate the number of bits to encode clusters, cores, and harts
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* from the original mhartid to a new dense index.
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*/
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#define NUM_OF_BITS_FOR_CLUSTERS 4
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#define NUM_OF_BITS_FOR_CORES 12
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#define NUM_OF_BITS_FOR_HARTS 4
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/* To get the field from new/hashed mhartid */
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#define NEW_CLUSTER_SHIFT (NUM_OF_BITS_FOR_CORES + NUM_OF_BITS_FOR_HARTS)
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#define NEW_CLUSTER_MASK ((1 << NUM_OF_BITS_FOR_CLUSTERS) - 1)
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#define NEW_CORE_SHIFT NUM_OF_BITS_FOR_HARTS
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#define NEW_CORE_MASK ((1 << NUM_OF_BITS_FOR_CORES) - 1)
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#define NEW_HART_MASK ((1 << NUM_OF_BITS_FOR_HARTS) - 1)
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#define cpu_cluster(i) (((i) >> NEW_CLUSTER_SHIFT) & NEW_CLUSTER_MASK)
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#define cpu_core(i) (((i) >> NEW_CORE_SHIFT) & NEW_CORE_MASK)
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#define cpu_hart(i) ((i) & NEW_HART_MASK)
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#define CPC_OFFSET (0x8000)
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#define SIZE_FOR_CPC_MTIME 0x10000 /* The size must be 2^order */
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#define AIA_OFFSET (0x40000)
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#define SIZE_FOR_AIA_M_MODE 0x20000 /* The size must be 2^order */
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#define P8700_ALIGN 0x10000
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#define CM_BASE_HART_SHIFT 3
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#define CM_BASE_CORE_SHIFT 8
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#define CM_BASE_CLUSTER_SHIFT 19
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/* GCR Block offsets */
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#define GCR_OFF_LOCAL 0x2000
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#define GCR_BASE_OFFSET 0x0008
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#define GCR_CORE_COH_EN 0x00f8
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#define GCR_CORE_COH_EN_EN (0x1 << 0)
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#define L2_PFT_CONTROL_OFFSET 0x0300
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#define L2_PFT_CONTROL_B_OFFSET 0x0308
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/* CPC Block offsets */
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#define CPC_PWRUP_CTL 0x0030
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#define CPC_CM_STAT_CONF 0x1008
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#define CPC_OFF_LOCAL 0x2000
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#define CPC_Cx_VP_STOP 0x0020
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#define CPC_Cx_VP_RUN 0x0028
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#define CPC_Cx_CMD 0x0000
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#define CPC_Cx_CMD_PWRUP 0x3
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#define CPC_Cx_CMD_RESET 0x4
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#define CPC_Cx_STAT_CONF 0x0008
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#define CPC_Cx_STAT_CONF_SEQ_STATE GEN_MASK(22, 19)
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U5 6
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U6 7
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#endif
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