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https://github.com/riscv-software-src/opensbi.git
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a9a9751185
We extend CLINT cold init function to have a "struct clint_data *" parameter pointing to CLINT details. This allows platforms to use CLINT functions for multiple CLINT instances. When multiple CLINTs are present, the platform can also provide one of the CLINT as reference CLINT for other CLINTs. This will help CLINTs to sync their time value with reference CLINT using a time_delta computed in warm init function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
152 lines
3.8 KiB
C
152 lines
3.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/sys/clint.h>
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#include "platform.h"
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static struct c910_regs_struct c910_regs;
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static struct clint_data clint = {
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.addr = 0, /* Updated at cold boot time */
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.first_hartid = 0,
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.hart_count = C910_HART_COUNT,
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.has_64bit_mmio = FALSE,
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};
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static int c910_early_init(bool cold_boot)
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{
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if (cold_boot) {
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/* Load from boot core */
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c910_regs.pmpaddr0 = csr_read(CSR_PMPADDR0);
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c910_regs.pmpaddr1 = csr_read(CSR_PMPADDR1);
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c910_regs.pmpaddr2 = csr_read(CSR_PMPADDR2);
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c910_regs.pmpaddr3 = csr_read(CSR_PMPADDR3);
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c910_regs.pmpaddr4 = csr_read(CSR_PMPADDR4);
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c910_regs.pmpaddr5 = csr_read(CSR_PMPADDR5);
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c910_regs.pmpaddr6 = csr_read(CSR_PMPADDR6);
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c910_regs.pmpaddr7 = csr_read(CSR_PMPADDR7);
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c910_regs.pmpcfg0 = csr_read(CSR_PMPCFG0);
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c910_regs.mcor = csr_read(CSR_MCOR);
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c910_regs.mhcr = csr_read(CSR_MHCR);
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c910_regs.mccr2 = csr_read(CSR_MCCR2);
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c910_regs.mhint = csr_read(CSR_MHINT);
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c910_regs.mxstatus = csr_read(CSR_MXSTATUS);
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c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE);
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c910_regs.clint_base_addr =
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c910_regs.plic_base_addr + C910_PLIC_CLINT_OFFSET;
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} else {
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/* Store to other core */
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csr_write(CSR_PMPADDR0, c910_regs.pmpaddr0);
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csr_write(CSR_PMPADDR1, c910_regs.pmpaddr1);
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csr_write(CSR_PMPADDR2, c910_regs.pmpaddr2);
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csr_write(CSR_PMPADDR3, c910_regs.pmpaddr3);
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csr_write(CSR_PMPADDR4, c910_regs.pmpaddr4);
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csr_write(CSR_PMPADDR5, c910_regs.pmpaddr5);
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csr_write(CSR_PMPADDR6, c910_regs.pmpaddr6);
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csr_write(CSR_PMPADDR7, c910_regs.pmpaddr7);
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csr_write(CSR_PMPCFG0, c910_regs.pmpcfg0);
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csr_write(CSR_MCOR, c910_regs.mcor);
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csr_write(CSR_MHCR, c910_regs.mhcr);
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csr_write(CSR_MHINT, c910_regs.mhint);
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csr_write(CSR_MXSTATUS, c910_regs.mxstatus);
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}
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return 0;
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}
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static int c910_final_init(bool cold_boot)
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{
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return 0;
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}
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static int c910_irqchip_init(bool cold_boot)
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{
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/* Delegate plic enable into S-mode */
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writel(C910_PLIC_DELEG_ENABLE,
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(void *)c910_regs.plic_base_addr + C910_PLIC_DELEG_OFFSET);
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return 0;
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}
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static int c910_ipi_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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clint.addr = c910_regs.clint_base_addr;
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rc = clint_cold_ipi_init(&clint);
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if (rc)
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return rc;
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}
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return clint_warm_ipi_init();
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}
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static int c910_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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clint.addr = c910_regs.clint_base_addr;
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ret = clint_cold_timer_init(&clint, NULL);
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if (ret)
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return ret;
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}
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return clint_warm_timer_init();
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}
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static int c910_system_reset(u32 type)
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{
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asm volatile ("ebreak");
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return 0;
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}
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int c910_hart_start(u32 hartid, ulong saddr)
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{
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csr_write(CSR_MRVBR, saddr);
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csr_write(CSR_MRMR, csr_read(CSR_MRMR) | (1 << hartid));
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return 0;
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}
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const struct sbi_platform_operations platform_ops = {
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.early_init = c910_early_init,
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.final_init = c910_final_init,
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.irqchip_init = c910_irqchip_init,
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.ipi_init = c910_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.timer_init = c910_timer_init,
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.timer_event_start = clint_timer_event_start,
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.system_reset = c910_system_reset,
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.hart_start = c910_hart_start,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "T-HEAD Xuantie c910",
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.features = SBI_THEAD_FEATURES,
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.hart_count = C910_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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