mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-06-17 16:41:19 +01:00
Bo Gan
a8be5e9478
Fix the following issues with misaligned vector load/store: a. Stack overflow: the mask[VLEN_MAX / 8] variable consumes 8K stack space, given VLEN_MAX=65536, overflowing the default-sized stack. There's no need to fetch the whole mask in one go, instead, make it on-demand. Use a 128-byte mask as local buffer to hold the sliding window of mask. For rvv load, this is allowed -- from the spec: "The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction" We don't need to worry about the mask getting overwritten. b. Maintain the value of vstart upon abort (uptrap) to avoid duplicate work. After fault resolution, the instruction can restart from the faulting vstart. For Fault-Only-First loads, reset vstart to 0, as previously done so, to conform to spec. c. Explicitly set VS dirty in VSSTATUS with SET_VS_DIRTY() if faulting from V=1, and if any vector register, including vstart/vl/vtype, gets changed in the handler. It can add 1 unnecessary op to set VS dirty in M/SSTATUS (not VSSTATUS), where the HW already did, but for code simplicity, do it anyway. The overhead should be negligible. Signed-off-by: Bo Gan <ganboing@gmail.com> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260609060024.706-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
395 lines
9.6 KiB
C
395 lines
9.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2024 SiFive Inc.
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*
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* Authors:
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* Andrew Waterman <andrew@sifive.com>
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* Nylon Chen <nylon.chen@sifive.com>
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* Zong Li <nylon.chen@sifive.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_trap_ldst.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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#include <sbi/sbi_vector.h>
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#ifdef OPENSBI_CC_SUPPORT_VECTOR
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#define MASK_BUFFLEN 1024
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static inline void set_vreg(ulong vlenb, ulong which,
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ulong pos, ulong size, const uint8_t *bytes)
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{
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pos += (which % 8) * vlenb;
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bytes -= pos;
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vsetvli x0, %0, e8, m8, tu, ma\n\t"
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" .option pop\n\t"
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:: "r" (pos + size));
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csr_write(CSR_VSTART, pos);
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switch (which / 8) {
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case 0:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vle8.v v0, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 1:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vle8.v v8, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 2:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vle8.v v16, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 3:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vle8.v v24, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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default:
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break;
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}
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}
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static inline void get_vreg(ulong vlenb, ulong which,
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ulong pos, ulong size, uint8_t *bytes)
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{
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pos += (which % 8) * vlenb;
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bytes -= pos;
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vsetvli x0, %0, e8, m8, tu, ma\n\t"
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" .option pop\n\t"
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:: "r" (pos + size));
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csr_write(CSR_VSTART, pos);
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switch (which / 8) {
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case 0:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vse8.v v0, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 1:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vse8.v v8, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 2:
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vse8.v v16, (%0)\n\t"
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" .option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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case 3:
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asm volatile (
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".option push\n\t"
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".option arch, +v\n\t"
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"vse8.v v24, (%0)\n\t"
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".option pop\n\t"
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:: "r" (bytes) : "memory");
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break;
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default:
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break;
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}
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}
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static inline void vsetvl(ulong vl, ulong vtype)
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{
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asm volatile (
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" .option push\n\t"
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" .option arch, +v\n\t"
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" vsetvl x0, %0, %1\n\t"
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" .option pop\n\t"
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:: "r" (vl), "r" (vtype));
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}
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/**
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* Handling of misaligned fault is done by a collection of smaller, but
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* aligned load/store(s). Another fault (load/store, page fault...) can
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* arise from any of them, then the handling gets aborted. We must fixup
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* the tinst to pretend the fault was rised from the original insn. For
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* vector insn, simply null out tinst if it's not a guest-page fault, as
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* there's no transformed insn for vector load/store
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*/
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static inline void sbi_misaligned_v_tinst_fixup(struct sbi_trap_info *uptrap)
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{
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/*
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* The function is called in code path for handling a vector
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* load/store misaligned fault, thus the new uptrap can't have
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* custom value of tinst
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*/
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if (uptrap->tinst == INSN_PSEUDO_VS_LOAD ||
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uptrap->tinst == INSN_PSEUDO_VS_STORE)
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/* Use uptrap as-is for guest-page faults */
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return;
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uptrap->tinst = 0;
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}
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int sbi_misaligned_v_ld_emulator(ulong insn, struct sbi_trap_context *tcntx)
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{
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struct sbi_trap_regs *regs = &tcntx->regs;
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struct sbi_trap_info uptrap;
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ulong vl = csr_read(CSR_VL);
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ulong vtype = csr_read(CSR_VTYPE);
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ulong vlenb = csr_read(CSR_VLENB);
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ulong vstart = csr_read(CSR_VSTART), orig_vstart = vstart;
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ulong base = GET_RS1(insn, regs);
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ulong stride = GET_RS2(insn, regs);
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ulong vd = GET_VD(insn);
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ulong vs2 = GET_VS2(insn);
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ulong view = GET_VIEW(insn);
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ulong vsew = GET_VSEW(vtype);
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ulong vlmul = GET_VLMUL(vtype);
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bool illegal = GET_MEW(insn);
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bool masked = IS_MASKED(insn);
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uint8_t mask[MASK_BUFFLEN / 8];
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uint8_t bytes[8 * sizeof(uint64_t)];
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ulong mask_len = MASK_BUFFLEN < vlenb * 8 ? MASK_BUFFLEN : vlenb * 8;
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ulong len = GET_LEN(view);
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ulong nf = GET_NF(insn);
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ulong vemul = GET_VEMUL(vlmul, view, vsew);
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ulong emul = GET_EMUL(vemul);
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if (IS_UNIT_STRIDE_LOAD(insn) || IS_FAULT_ONLY_FIRST_LOAD(insn)) {
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stride = nf * len;
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} else if (IS_WHOLE_REG_LOAD(insn)) {
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vl = (nf * vlenb) >> view;
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nf = 1;
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vemul = 0;
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emul = 1;
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stride = nf * len;
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} else if (IS_INDEXED_LOAD(insn)) {
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len = 1 << vsew;
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vemul = (vlmul + vsew - vsew) & 7;
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emul = 1 << ((vemul & 4) ? 0 : vemul);
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stride = nf * len;
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}
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if (illegal) {
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struct sbi_trap_info trap = {
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uptrap.cause = CAUSE_ILLEGAL_INSTRUCTION,
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uptrap.tval = insn,
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};
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return sbi_trap_redirect(regs, &trap);
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}
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do {
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if (masked) {
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if (vstart == orig_vstart || vstart % mask_len == 0)
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/* Fetch a mask_len chunk of mask */
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get_vreg(vlenb, 0, vstart / mask_len * mask_len,
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mask_len, mask);
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if (~mask[vstart % mask_len / 8] & BIT(vstart % 8))
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continue;
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}
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/* compute element address */
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ulong addr = base + vstart * stride;
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if (IS_INDEXED_LOAD(insn)) {
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ulong offset = 0;
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get_vreg(vlenb, vs2, vstart << view, 1 << view, (uint8_t *)&offset);
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addr = base + offset;
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}
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csr_write(CSR_VSTART, vstart);
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/* obtain load data from memory */
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for (ulong seg = 0; seg < nf; seg++) {
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sbi_load_loop(bytes + seg * len,
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addr + seg * len, len, &uptrap);
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if (!uptrap.cause)
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continue;
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if (IS_FAULT_ONLY_FIRST_LOAD(insn) && vstart != 0) {
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vl = vstart;
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goto done;
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}
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vsetvl(vl, vtype);
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csr_write(CSR_VSTART, vstart);
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/* Don't forget to set dirty if vstart has changed */
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if (vstart != orig_vstart)
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SET_VS_DIRTY(regs);
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sbi_misaligned_v_tinst_fixup(&uptrap);
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return sbi_trap_redirect(regs, &uptrap);
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}
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/* write load data to regfile */
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for (ulong seg = 0; seg < nf; seg++)
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set_vreg(vlenb, vd + seg * emul, vstart * len,
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len, &bytes[seg * len]);
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} while (++vstart < vl);
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done:
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/* restore clobbered vl/vtype */
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vsetvl(vl, vtype); // VSTART resets to 0
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/*
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* At least 1 element is processed, or vl is changed above in
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* the FAULT_ONLY_FIRST_LOAD path, thus set dirty.
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*/
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SET_VS_DIRTY(regs);
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/* Return a >0 value for the caller to advance mepc */
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return 1;
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}
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int sbi_misaligned_v_st_emulator(ulong insn, struct sbi_trap_context *tcntx)
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{
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struct sbi_trap_regs *regs = &tcntx->regs;
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struct sbi_trap_info uptrap;
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ulong vl = csr_read(CSR_VL);
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ulong vtype = csr_read(CSR_VTYPE);
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ulong vlenb = csr_read(CSR_VLENB);
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ulong vstart = csr_read(CSR_VSTART), orig_vstart = vstart;
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ulong base = GET_RS1(insn, regs);
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ulong stride = GET_RS2(insn, regs);
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ulong vd = GET_VD(insn);
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ulong vs2 = GET_VS2(insn);
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ulong view = GET_VIEW(insn);
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ulong vsew = GET_VSEW(vtype);
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ulong vlmul = GET_VLMUL(vtype);
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bool illegal = GET_MEW(insn);
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bool masked = IS_MASKED(insn);
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uint8_t mask[MASK_BUFFLEN / 8];
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uint8_t bytes[8 * sizeof(uint64_t)];
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ulong mask_len = MASK_BUFFLEN < vlenb * 8 ? MASK_BUFFLEN : vlenb * 8;
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ulong len = GET_LEN(view);
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ulong nf = GET_NF(insn);
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ulong vemul = GET_VEMUL(vlmul, view, vsew);
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ulong emul = GET_EMUL(vemul);
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if (IS_UNIT_STRIDE_STORE(insn)) {
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stride = nf * len;
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} else if (IS_WHOLE_REG_STORE(insn)) {
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vl = (nf * vlenb) >> view;
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nf = 1;
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vemul = 0;
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emul = 1;
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stride = nf * len;
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} else if (IS_INDEXED_STORE(insn)) {
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len = 1 << vsew;
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vemul = (vlmul + vsew - vsew) & 7;
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emul = 1 << ((vemul & 4) ? 0 : vemul);
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stride = nf * len;
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}
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if (illegal) {
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struct sbi_trap_info trap = {
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uptrap.cause = CAUSE_ILLEGAL_INSTRUCTION,
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uptrap.tval = insn,
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};
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return sbi_trap_redirect(regs, &trap);
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}
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do {
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if (masked) {
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if (vstart == orig_vstart || vstart % mask_len == 0)
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/* Fetch a mask_len chunk of mask */
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get_vreg(vlenb, 0, vstart / mask_len * mask_len,
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mask_len, mask);
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if (~mask[vstart % mask_len / 8] & BIT(vstart % 8))
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continue;
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}
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/* compute element address */
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ulong addr = base + vstart * stride;
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if (IS_INDEXED_STORE(insn)) {
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ulong offset = 0;
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get_vreg(vlenb, vs2, vstart << view, 1 << view, (uint8_t *)&offset);
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addr = base + offset;
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}
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/* obtain store data from regfile */
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for (ulong seg = 0; seg < nf; seg++)
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get_vreg(vlenb, vd + seg * emul, vstart * len,
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len, &bytes[seg * len]);
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/* write store data to memory */
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for (ulong seg = 0; seg < nf; seg++) {
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sbi_store_loop(bytes + seg * len,
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addr + seg * len, len, &uptrap);
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if (!uptrap.cause)
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continue;
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vsetvl(vl, vtype);
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csr_write(CSR_VSTART, vstart);
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/* Don't forget to set dirty if vstart has changed */
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if (vstart != orig_vstart)
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SET_VS_DIRTY(regs);
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sbi_misaligned_v_tinst_fixup(&uptrap);
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return sbi_trap_redirect(regs, &uptrap);
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}
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} while (++vstart < vl);
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/* restore clobbered vl/vtype */
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vsetvl(vl, vtype); // VSTART resets to 0
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/*
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* No need to set dirty for memory store, but as VSTART resets to
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* 0 above, need to set dirty if it's originally not 0.
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*/
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if (orig_vstart != 0)
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SET_VS_DIRTY(regs);
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/* Return a >0 value for the caller to advance mepc */
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return 1;
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}
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#else
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int sbi_misaligned_v_ld_emulator(ulong insn, struct sbi_trap_context *tcntx)
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{
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/* Unable to emulate, send trap to previous mode. */
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return sbi_trap_redirect(&tcntx->regs, &tcntx->trap);
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}
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int sbi_misaligned_v_st_emulator(ulong insn, struct sbi_trap_context *tcntx)
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{
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/* Unable to emulate, send trap to previous mode. */
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return sbi_trap_redirect(&tcntx->regs, &tcntx->trap);
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}
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#endif /* OPENSBI_CC_SUPPORT_VECTOR */
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