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bd74931d79
The old scheme doesn't allow sending hart0 self-IPI as the
corresponding bit on pending register is hardwired to 0, this
could lead to unhandle IPIs on SMP systems, esp. on single-core.
Furthermore, the limitation of old scheme is 8-core, instead of
reserving source hart information, we assign bit (x + 1) as the
enable and pending bit of hartx, this also expands the bootable
hart number.
The following diagram shows the enable bits of the new scheme
on 32-core Andes platform.
Pending regs: 0x1000 x---0---0---0---0------0---0
Pending hart ID: 0 1 2 3 ... 30 31
Interrupt ID: 0 1 2 3 4 ... 31 32
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Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
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0x2080 x---0---1---0---0-...--0---0---> hart1
| | | | | | |
0x2100 x---0---0---1---0-...--0---0---> hart2
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0x2180 x---0---0---0---1-...--0---0---> hart3
. . . . . . .
. . . . . . .
. . . . . . .
0x2f00 x---0---0---0---0-...--1---0---> hart30
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0x2f80 x---0---0---0---0-...--0---1---> hart31
<-------- word 0 -------><--- word 1 --->
To send IPI to hart0, for example, another hart (including hart0
itself) will set bit 1 of first word on the pending register.
We also fix indentation in andes_plicsw.h along with this patch.
Fixes: ce7c490719 ("lib: utils/ipi: Add Andes fdt ipi driver support")
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
116 lines
2.8 KiB
C
116 lines
2.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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* Leo Yu-Chi Liang <ycliang@andestech.com>
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi_utils/ipi/andes_plicsw.h>
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struct plicsw_data plicsw;
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static void plicsw_ipi_send(u32 hart_index)
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{
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ulong pending_reg;
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u32 interrupt_id, word_index, pending_bit;
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u32 target_hart = sbi_hartindex_to_hartid(hart_index);
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if (plicsw.hart_count <= target_hart)
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ebreak();
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/*
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* We assign a single bit for each hart.
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* Bit 0 is hardwired to 0, thus unavailable.
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* Bit(X+1) indicates that IPI is sent to hartX.
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*/
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interrupt_id = target_hart + 1;
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word_index = interrupt_id / 32;
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pending_bit = interrupt_id % 32;
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pending_reg = plicsw.addr + PLICSW_PENDING_BASE + word_index * 4;
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/* Set target hart's mip.MSIP */
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writel_relaxed(BIT(pending_bit), (void *)pending_reg);
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}
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static void plicsw_ipi_clear(u32 hart_index)
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{
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u32 target_hart = sbi_hartindex_to_hartid(hart_index);
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ulong reg = plicsw.addr + PLICSW_CONTEXT_BASE + PLICSW_CONTEXT_CLAIM +
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PLICSW_CONTEXT_STRIDE * target_hart;
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if (plicsw.hart_count <= target_hart)
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ebreak();
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/* Claim */
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u32 source = readl((void *)reg);
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/* A successful claim will clear mip.MSIP */
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/* Complete */
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writel(source, (void *)reg);
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}
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static struct sbi_ipi_device plicsw_ipi = {
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.name = "andes_plicsw",
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.ipi_send = plicsw_ipi_send,
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.ipi_clear = plicsw_ipi_clear
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};
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int plicsw_warm_ipi_init(void)
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{
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u32 hartid = current_hartid();
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/* Clear PLICSW IPI */
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plicsw_ipi_clear(hartid);
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return 0;
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}
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int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
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{
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int rc;
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u32 interrupt_id, word_index, enable_bit;
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ulong enable_reg, priority_reg;
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/* Setup source priority */
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for (int i = 0; i < plicsw->hart_count; i++) {
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priority_reg = plicsw->addr + PLICSW_PRIORITY_BASE + i * 4;
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writel(1, (void *)priority_reg);
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}
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/*
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* Setup enable for each hart, skip non-existent interrupt ID 0
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* which is hardwired to 0.
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*/
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for (int i = 0; i < plicsw->hart_count; i++) {
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interrupt_id = i + 1;
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word_index = interrupt_id / 32;
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enable_bit = interrupt_id % 32;
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enable_reg = plicsw->addr + PLICSW_ENABLE_BASE +
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PLICSW_ENABLE_STRIDE * i + 4 * word_index;
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writel(BIT(enable_bit), (void *)enable_reg);
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}
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/* Add PLICSW region to the root domain */
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rc = sbi_domain_root_add_memrange(plicsw->addr, plicsw->size,
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PLICSW_REGION_ALIGN,
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SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE);
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if (rc)
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return rc;
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sbi_ipi_set_device(&plicsw_ipi);
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return 0;
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}
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