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3669153e06
The TLB entries remain functional all the time once added in T-HEAD th1520 and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there are some stale TLB entries that contains the address of SBI, it will cause unexpected memory access and issue a illegal instruction error. To avoid this, a TLB flush is needed to drop these TLB entries before any memory access in the trap handler. To handle this workaroud, add a custom trap handler with executing TLB flush first in the T-HEAD platform to fix affected socs. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>