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https://github.com/riscv-software-src/opensbi.git
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a07402ac9c
We should not change trap->tval to mepc because mtval already points to the faulting portion of the emulated instruction fetch, which is also what stval is expected to be. In addition, htinst is only allowed to be zero for instruction access faults or page faults, and is only allowed to be zero or a psuedoinstruction for instruction guest-page faults. Fix trap->tinst for these cases. Signed-off-by: dramforever <dramforever@live.com> Reviewed-by: Anup Patel <anup@brainfault.org>
170 lines
6.1 KiB
C
170 lines
6.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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/**
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* a3 must a pointer to the sbi_trap_info and a4 is used as a temporary
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* register in the trap handler. Make sure that compiler doesn't use a3 & a4.
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*/
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#define DEFINE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \
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type sbi_load_##type(const type *addr, \
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struct sbi_trap_info *trap) \
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{ \
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register ulong tinfo asm("a3"); \
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register ulong mstatus = 0; \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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type ret = 0; \
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trap->cause = 0; \
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asm volatile( \
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"add %[tinfo], %[taddr], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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"csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n" \
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".option push\n" \
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".option norvc\n" \
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#insn " %[ret], %[addr]\n" \
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".option pop\n" \
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]\n" \
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"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
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: [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec), \
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[tinfo] "+&r"(tinfo), [ret] "=&r"(ret) \
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: [addr] "m"(*addr), [mprv] "r"(MSTATUS_MPRV), \
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[taddr] "r"((ulong)trap) \
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: "a4", "memory"); \
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return ret; \
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}
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#define DEFINE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \
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void sbi_store_##type(type *addr, type val, \
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struct sbi_trap_info *trap) \
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{ \
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register ulong tinfo asm("a3") = (ulong)trap; \
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register ulong mstatus = 0; \
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register ulong mtvec = sbi_hart_expected_trap_addr(); \
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trap->cause = 0; \
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asm volatile( \
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"add %[tinfo], %[taddr], zero\n" \
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
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"csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n" \
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".option push\n" \
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".option norvc\n" \
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#insn " %[val], %[addr]\n" \
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".option pop\n" \
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]\n" \
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"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
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: [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec), \
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[tinfo] "+&r"(tinfo) \
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: [addr] "m"(*addr), [mprv] "r"(MSTATUS_MPRV), \
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[val] "r"(val), [taddr] "r"((ulong)trap) \
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: "a4", "memory"); \
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}
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
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#if __riscv_xlen == 64
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
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DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
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#elif __riscv_xlen == 32
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
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DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
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u64 sbi_load_u64(const u64 *addr,
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struct sbi_trap_info *trap)
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{
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u64 ret = sbi_load_u32((u32 *)addr, trap);
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if (trap->cause)
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return 0;
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ret |= ((u64)sbi_load_u32((u32 *)addr + 1, trap) << 32);
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if (trap->cause)
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return 0;
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return ret;
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}
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void sbi_store_u64(u64 *addr, u64 val,
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struct sbi_trap_info *trap)
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{
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sbi_store_u32((u32 *)addr, val, trap);
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if (trap->cause)
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return;
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sbi_store_u32((u32 *)addr + 1, val >> 32, trap);
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if (trap->cause)
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return;
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}
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#else
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# error "Unexpected __riscv_xlen"
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#endif
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ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
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{
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register ulong tinfo asm("a3");
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register ulong ttmp asm("a4");
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register ulong mstatus = 0;
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register ulong mtvec = sbi_hart_expected_trap_addr();
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ulong insn = 0;
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trap->cause = 0;
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asm volatile(
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"add %[tinfo], %[taddr], zero\n"
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"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"
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"csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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"lhu %[insn], (%[addr])\n"
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"andi %[ttmp], %[insn], 3\n"
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"addi %[ttmp], %[ttmp], -3\n"
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"bne %[ttmp], zero, 2f\n"
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"lhu %[ttmp], 2(%[addr])\n"
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"sll %[ttmp], %[ttmp], 16\n"
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"add %[insn], %[insn], %[ttmp]\n"
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"2: csrw " STR(CSR_MSTATUS) ", %[mstatus]\n"
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"csrw " STR(CSR_MTVEC) ", %[mtvec]"
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: [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec),
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[tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp),
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[insn] "=&r"(insn)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR),
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[taddr] "r"((ulong)trap), [addr] "r"(mepc)
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: "memory");
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switch (trap->cause) {
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case CAUSE_LOAD_ACCESS:
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trap->cause = CAUSE_FETCH_ACCESS;
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trap->tinst = 0UL;
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break;
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case CAUSE_LOAD_PAGE_FAULT:
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trap->cause = CAUSE_FETCH_PAGE_FAULT;
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trap->tinst = 0UL;
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break;
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case CAUSE_LOAD_GUEST_PAGE_FAULT:
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trap->cause = CAUSE_FETCH_GUEST_PAGE_FAULT;
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if (trap->tinst != INSN_PSEUDO_VS_LOAD &&
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trap->tinst != INSN_PSEUDO_VS_STORE)
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trap->tinst = 0UL;
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break;
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default:
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break;
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};
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return insn;
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}
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