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Allwinner D1 contains a "PPU" power domain controller which can automatically power down/up the CPU power domain. This power domain includes the C906 core along with its CLINT and PLIC. This HSM implementation supports non-retentive hart suspend by: 1) Saving/restoring state that is lost during hart suspend, 2) Performing cache maintenance before/after hart suspend, 3) Configuring wakeup sources before hart suspend, and 4) Asking the PPU to power down the hart when it enters WFI. Since this HSM implementation is for a single-core SoC, it does not need to worry about concurrency or saving multiple instances of state. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
7 lines
134 B
Makefile
7 lines
134 B
Makefile
#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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carray-platform_override_modules-y += sun20i_d1
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platform-objs-y += allwinner/sun20i-d1.o
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