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8e941e7fe3
Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Authors:
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* Inochi Amaoto <inochiama@outlook.com>
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* Haijiao Liu <haijiao.liu@sophgo.com>
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*
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*/
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#include <thead/c9xx_encoding.h>
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#include <thead/c9xx_pmu.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_pmu.h>
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static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
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{
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if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
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return;
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/**
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* Clear out the OF bit so that next interrupt can be enabled.
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* This should be done before starting interrupt to avoid unexcepted
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* overflow interrupt.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
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/**
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* This register is described in C9xx document as the control register
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* for enabling writes to the superuser state counter. However, if the
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* corresponding bit is not set to 1, scounterof will always read as 0
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* when the counter register overflows.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
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/**
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* SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
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* while the C9XX has designated enable bits.
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* So enable per-counter interrupt on C9xx here.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
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{
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/**
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* There is no need to clear the bit of mcounterwen, it will expire
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* after setting the csr mcountinhibit.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static int thead_c9xx_pmu_irq_bit(void)
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{
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return THEAD_C9XX_MIP_MOIP;
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}
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static const struct sbi_pmu_device thead_c9xx_pmu_device = {
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.name = "thead,c900-pmu",
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.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
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.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
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.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
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};
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void thead_c9xx_register_pmu_device(void)
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{
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sbi_pmu_set_device(&thead_c9xx_pmu_device);
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}
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