mirror of
https://github.com/riscv-software-src/opensbi.git
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8c362e7d06
This simplifies both the callers and the callees by removing duplicated
code and consolidating the error handling. It also fixes two bugs in the
process:
1) ie_words was one too large when plic->num_src was a multiple of 32.
2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA
platforms previously only enabled one out of every 32 interrupts.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
105 lines
2.3 KiB
C
105 lines
2.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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* Samuel Holland <samuel@sholland.org>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_string.h>
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#include <sbi_utils/irqchip/plic.h>
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#define PLIC_PRIORITY_BASE 0x0
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#define PLIC_PENDING_BASE 0x1000
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#define PLIC_ENABLE_BASE 0x2000
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#define PLIC_ENABLE_STRIDE 0x80
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#define PLIC_CONTEXT_BASE 0x200000
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#define PLIC_CONTEXT_STRIDE 0x1000
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static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
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{
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volatile void *plic_priority = (char *)plic->addr +
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PLIC_PRIORITY_BASE + 4 * source;
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writel(val, plic_priority);
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}
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static void plic_set_thresh(const struct plic_data *plic, u32 cntxid, u32 val)
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{
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volatile void *plic_thresh;
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plic_thresh = (char *)plic->addr +
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PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
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writel(val, plic_thresh);
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}
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static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
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u32 word_index, u32 val)
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{
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volatile char *plic_ie;
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plic_ie = (char *)plic->addr +
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PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
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writel(val, plic_ie + word_index * 4);
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}
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int plic_context_init(const struct plic_data *plic, int context_id,
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bool enable, u32 threshold)
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{
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u32 ie_words, ie_value;
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if (!plic || context_id < 0)
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return SBI_EINVAL;
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ie_words = (plic->num_src + 31) / 32;
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ie_value = enable ? 0xffffffffU : 0U;
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for (u32 i = 0; i < ie_words; i++)
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plic_set_ie(plic, context_id, i, ie_value);
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plic_set_thresh(plic, context_id, threshold);
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return 0;
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}
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int plic_warm_irqchip_init(const struct plic_data *plic,
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int m_cntx_id, int s_cntx_id)
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{
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int ret;
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/* By default, disable all IRQs for M-mode of target HART */
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if (m_cntx_id > -1) {
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ret = plic_context_init(plic, m_cntx_id, false, 0x7);
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if (ret)
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return ret;
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}
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/* By default, disable all IRQs for S-mode of target HART */
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if (s_cntx_id > -1) {
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ret = plic_context_init(plic, m_cntx_id, false, 0x7);
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if (ret)
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return ret;
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}
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return 0;
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}
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int plic_cold_irqchip_init(const struct plic_data *plic)
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{
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int i;
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if (!plic)
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return SBI_EINVAL;
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/* Configure default priorities of all IRQs */
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for (i = 1; i <= plic->num_src; i++)
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plic_set_priority(plic, i, 0);
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return 0;
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}
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