mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 23:41:23 +01:00
8b1617d13a
This commit provides basic support for the Renesas RZ/Five (R9A07G043F) SoC. The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP) 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include: - Gigabit Ethernet 2ch - CAN interface (CAN-FD) 2ch - USB 2.0 interface 2ch - SD interface 2ch - AD converter 2ch Useful links: ------------- Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>
38 lines
961 B
Plaintext
38 lines
961 B
Plaintext
CONFIG_PLATFORM_ALLWINNER_D1=y
|
|
CONFIG_PLATFORM_ANDES_AE350=y
|
|
CONFIG_PLATFORM_RENESAS_RZFIVE=y
|
|
CONFIG_PLATFORM_SIFIVE_FU540=y
|
|
CONFIG_PLATFORM_SIFIVE_FU740=y
|
|
CONFIG_FDT_GPIO=y
|
|
CONFIG_FDT_GPIO_SIFIVE=y
|
|
CONFIG_FDT_I2C=y
|
|
CONFIG_FDT_I2C_SIFIVE=y
|
|
CONFIG_FDT_IPI=y
|
|
CONFIG_FDT_IPI_MSWI=y
|
|
CONFIG_FDT_IPI_PLICSW=y
|
|
CONFIG_FDT_IRQCHIP=y
|
|
CONFIG_FDT_IRQCHIP_APLIC=y
|
|
CONFIG_FDT_IRQCHIP_IMSIC=y
|
|
CONFIG_FDT_IRQCHIP_PLIC=y
|
|
CONFIG_FDT_RESET=y
|
|
CONFIG_FDT_RESET_ATCWDT200=y
|
|
CONFIG_FDT_RESET_GPIO=y
|
|
CONFIG_FDT_RESET_HTIF=y
|
|
CONFIG_FDT_RESET_SIFIVE_TEST=y
|
|
CONFIG_FDT_RESET_SUNXI_WDT=y
|
|
CONFIG_FDT_RESET_THEAD=y
|
|
CONFIG_FDT_SERIAL=y
|
|
CONFIG_FDT_SERIAL_CADENCE=y
|
|
CONFIG_FDT_SERIAL_GAISLER=y
|
|
CONFIG_FDT_SERIAL_HTIF=y
|
|
CONFIG_FDT_SERIAL_RENESAS_SCIF=y
|
|
CONFIG_FDT_SERIAL_SHAKTI=y
|
|
CONFIG_FDT_SERIAL_SIFIVE=y
|
|
CONFIG_FDT_SERIAL_LITEX=y
|
|
CONFIG_FDT_SERIAL_UART8250=y
|
|
CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
|
|
CONFIG_FDT_TIMER=y
|
|
CONFIG_FDT_TIMER_MTIMER=y
|
|
CONFIG_FDT_TIMER_PLMT=y
|
|
CONFIG_SERIAL_SEMIHOSTING=y
|