Files
opensbi/platform/fpga/ariane/platform.c
Anup Patel 85f22b38c8 include: sbi: Remove platform specific IPI init
The platform specfic IPI init is not need anymore because using
IPI device rating multiple IPI devices can be registered in any
order as part of the platform specific early init.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Nick Hu <nick.hu@sifive.com>
Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16 09:56:31 +05:30

144 lines
3.5 KiB
C

/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2019 FORTH-ICS/CARV
* Panagiotis Peristerakis <perister@ics.forth.gr>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_const.h>
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/ipi/aclint_mswi.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/uart8250.h>
#include <sbi_utils/timer/aclint_mtimer.h>
#define ARIANE_UART_ADDR 0x10000000
#define ARIANE_UART_FREQ 50000000
#define ARIANE_UART_BAUDRATE 115200
#define ARIANE_UART_REG_SHIFT 2
#define ARIANE_UART_REG_WIDTH 4
#define ARIANE_UART_REG_OFFSET 0
#define ARIANE_UART_CAPS 0
#define ARIANE_PLIC_ADDR 0xc000000
#define ARIANE_PLIC_SIZE (0x200000 + \
(ARIANE_HART_COUNT * 0x1000))
#define ARIANE_PLIC_NUM_SOURCES 3
#define ARIANE_HART_COUNT 1
#define ARIANE_CLINT_ADDR 0x2000000
#define ARIANE_ACLINT_MTIMER_FREQ 1000000
#define ARIANE_ACLINT_MSWI_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MSWI_OFFSET)
#define ARIANE_ACLINT_MTIMER_ADDR (ARIANE_CLINT_ADDR + \
CLINT_MTIMER_OFFSET)
static struct plic_data plic = {
.addr = ARIANE_PLIC_ADDR,
.size = ARIANE_PLIC_SIZE,
.num_src = ARIANE_PLIC_NUM_SOURCES,
.flags = PLIC_FLAG_ARIANE_BUG,
.context_map = {
[0] = { 0, 1 },
},
};
static struct aclint_mswi_data mswi = {
.addr = ARIANE_ACLINT_MSWI_ADDR,
.size = ACLINT_MSWI_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
};
static struct aclint_mtimer_data mtimer = {
.mtime_freq = ARIANE_ACLINT_MTIMER_FREQ,
.mtime_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIME_OFFSET,
.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
.mtimecmp_addr = ARIANE_ACLINT_MTIMER_ADDR +
ACLINT_DEFAULT_MTIMECMP_OFFSET,
.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
.first_hartid = 0,
.hart_count = ARIANE_HART_COUNT,
.has_64bit_mmio = true,
};
/*
* Ariane platform early initialization.
*/
static int ariane_early_init(bool cold_boot)
{
int rc;
if (!cold_boot)
return 0;
rc = uart8250_init(ARIANE_UART_ADDR,
ARIANE_UART_FREQ,
ARIANE_UART_BAUDRATE,
ARIANE_UART_REG_SHIFT,
ARIANE_UART_REG_WIDTH,
ARIANE_UART_REG_OFFSET,
ARIANE_UART_CAPS);
if (rc)
return rc;
return aclint_mswi_cold_init(&mswi);
}
/*
* Ariane platform final initialization.
*/
static int ariane_final_init(bool cold_boot)
{
void *fdt;
if (!cold_boot)
return 0;
fdt = fdt_get_address_rw();
fdt_fixups(fdt);
return 0;
}
/*
* Initialize the ariane interrupt controller during cold boot.
*/
static int ariane_irqchip_init(void)
{
return plic_cold_irqchip_init(&plic);
}
/*
* Initialize ariane timer during cold boot.
*/
static int ariane_timer_init(void)
{
return aclint_mtimer_cold_init(&mtimer, NULL);
}
/*
* Platform descriptor.
*/
const struct sbi_platform_operations platform_ops = {
.early_init = ariane_early_init,
.final_init = ariane_final_init,
.irqchip_init = ariane_irqchip_init,
.timer_init = ariane_timer_init,
};
const struct sbi_platform platform = {
.opensbi_version = OPENSBI_VERSION,
.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
.name = "ARIANE RISC-V",
.features = SBI_PLATFORM_DEFAULT_FEATURES,
.hart_count = ARIANE_HART_COUNT,
.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
.heap_size = SBI_PLATFORM_DEFAULT_HEAP_SIZE(ARIANE_HART_COUNT),
.platform_ops_addr = (unsigned long)&platform_ops
};