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Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
169 lines
4.1 KiB
C
169 lines
4.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Andes Technology Corporation
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*/
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#include <andes/andes.h>
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#include <libfdt.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_init.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi_utils/fdt/fdt_driver.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/hsm/fdt_hsm_andes_atcsmu.h>
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static unsigned long atcsmu_base;
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void atcsmu_set_wakeup_events(u32 events, u32 hartid)
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{
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writel_relaxed(events, (char *)atcsmu_base + PCSm_WE_OFFSET(hartid));
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}
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bool atcsmu_support_sleep_mode(u32 sleep_type, u32 hartid)
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{
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u32 pcs_cfg;
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u32 mask;
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const char *sleep_mode;
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pcs_cfg = readl_relaxed((char *)atcsmu_base + PCSm_CFG_OFFSET(hartid));
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switch (sleep_type) {
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case SBI_SUSP_AE350_LIGHT_SLEEP:
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mask = PCS_CFG_LIGHT_SLEEP;
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sleep_mode = "light sleep";
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break;
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case SBI_SUSP_SLEEP_TYPE_SUSPEND:
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mask = PCS_CFG_DEEP_SLEEP;
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sleep_mode = "deep sleep";
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break;
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default:
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return false;
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}
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if (!EXTRACT_FIELD(pcs_cfg, mask)) {
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sbi_printf("ATCSMU: hart%d (PCS%d) does not support %s mode\n",
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hartid, hartid + 3, sleep_mode);
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return false;
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}
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return true;
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}
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void atcsmu_set_command(u32 pcs_ctl, u32 hartid)
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{
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writel_relaxed(pcs_ctl, (char *)atcsmu_base + PCSm_CTL_OFFSET(hartid));
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}
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int atcsmu_set_reset_vector(u64 wakeup_addr, u32 hartid)
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{
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u32 vec_lo;
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u32 vec_hi;
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u64 reset_vector;
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writel((u32)wakeup_addr, (char *)atcsmu_base + HARTn_RESET_VEC_LO(hartid));
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writel((u32)(wakeup_addr >> 32), (char *)atcsmu_base + HARTn_RESET_VEC_HI(hartid));
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vec_lo = readl((char *)atcsmu_base + HARTn_RESET_VEC_LO(hartid));
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vec_hi = readl((char *)atcsmu_base + HARTn_RESET_VEC_HI(hartid));
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reset_vector = (u64)vec_hi << 32 | vec_lo;
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if (reset_vector != wakeup_addr) {
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sbi_printf("ATCSMU: hart%d (PCS%d): failed to program the reset vector\n",
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hartid, hartid + 3);
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return SBI_EFAIL;
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}
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return SBI_OK;
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}
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u32 atcsmu_get_sleep_type(u32 hartid)
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{
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return readl_relaxed((char *)atcsmu_base + PCSm_SCRATCH_OFFSET(hartid));
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}
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static int ae350_hart_start(u32 hartid, ulong saddr)
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{
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u32 hartindex = sbi_hartid_to_hartindex(hartid);
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/*
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* Don't send wakeup command when:
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* 1) boot time
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* 2) the target hart is non-sleepable 25-series hart0
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*/
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if (!sbi_init_count(hartindex) || (is_andes(25) && hartid == 0))
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return sbi_ipi_raw_send(hartindex, false);
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atcsmu_set_command(WAKEUP_CMD, hartid);
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return 0;
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}
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static int ae350_hart_stop(void)
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{
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u32 hartid = current_hartid();
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u32 sleep_type = atcsmu_get_sleep_type(hartid);
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int rc;
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/*
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* For Andes AX25MP, the hart0 shares power domain with the last level
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* cache. Instead of turning it off, it should fall through and jump to
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* warmboot_addr.
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*/
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if (is_andes(25) && hartid == 0)
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return SBI_ENOTSUPP;
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if (!atcsmu_support_sleep_mode(sleep_type, hartid))
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return SBI_ENOTSUPP;
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/* Prevent the core leaving the WFI mode unexpectedly */
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csr_write(CSR_MIE, 0);
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atcsmu_set_wakeup_events(0x0, hartid);
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atcsmu_set_command(DEEP_SLEEP_CMD, hartid);
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rc = atcsmu_set_reset_vector((ulong)ae350_enable_coherency_warmboot, hartid);
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if (rc)
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return SBI_EFAIL;
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ae350_non_ret_save(sbi_scratch_thishart_ptr());
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ae350_disable_coherency();
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wfi();
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return 0;
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}
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static const struct sbi_hsm_device hsm_andes_atcsmu = {
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.name = "andes_atcsmu",
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.hart_start = ae350_hart_start,
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.hart_stop = ae350_hart_stop,
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};
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static int hsm_andes_atcsmu_probe(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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int poff, rc;
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u64 addr;
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/* Need to find the parent for the address property */
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poff = fdt_parent_offset(fdt, nodeoff);
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if (poff < 0)
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return SBI_EINVAL;
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rc = fdt_get_node_addr_size(fdt, poff, 0, &addr, NULL);
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if (rc < 0 || !addr)
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return SBI_ENODEV;
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atcsmu_base = addr;
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sbi_hsm_set_device(&hsm_andes_atcsmu);
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return 0;
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}
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static const struct fdt_match hsm_andes_atcsmu_match[] = {
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{ .compatible = "andestech,atcsmu-hsm" },
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{ },
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};
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const struct fdt_driver fdt_hsm_andes_atcsmu = {
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.match_table = hsm_andes_atcsmu_match,
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.init = hsm_andes_atcsmu_probe,
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};
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