mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 15:31:22 +01:00
111772353f
In addition to saving some code size, this moves the decision about setting the top-level external interrupt handler to the irqchip core, not the specific driver, which would be needed to support chained interrupt handlers. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
67 lines
1.2 KiB
C
67 lines
1.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_platform.h>
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static SBI_LIST_HEAD(irqchip_list);
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static int default_irqfn(void)
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{
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return SBI_ENODEV;
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}
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static int (*ext_irqfn)(void) = default_irqfn;
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int sbi_irqchip_process(void)
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{
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return ext_irqfn();
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}
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void sbi_irqchip_add_device(struct sbi_irqchip_device *dev)
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{
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sbi_list_add_tail(&dev->node, &irqchip_list);
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if (dev->irq_handle)
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ext_irqfn = dev->irq_handle;
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}
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int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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{
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int rc;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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struct sbi_irqchip_device *dev;
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if (cold_boot) {
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rc = sbi_platform_irqchip_init(plat);
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if (rc)
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return rc;
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}
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sbi_list_for_each_entry(dev, &irqchip_list, node) {
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if (!dev->warm_init)
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continue;
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rc = dev->warm_init(dev);
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if (rc)
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return rc;
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}
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if (ext_irqfn != default_irqfn)
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csr_set(CSR_MIE, MIP_MEIP);
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return 0;
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}
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void sbi_irqchip_exit(struct sbi_scratch *scratch)
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{
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if (ext_irqfn != default_irqfn)
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csr_clear(CSR_MIE, MIP_MEIP);
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}
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