mirror of
https://github.com/riscv-software-src/opensbi.git
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f82c4bdf8c
Most CSRs are XLEN bits wide, but some are 64 bit, so rv32 needs two accesses, plaguing the code with ifdefs. Add new helpers that split 64 bit operation into two operations on rv32. The helpers don't use "csr + 0x10", but append "H" at the end of the csr name to get a compile-time error when accessing a non 64 bit register. This has the downside that you have to use the name when accessing them. e.g. csr_read64(0x1234) or csr_read64(CSR_SATP) won't compile and the error messages you get for these bugs are not straightforward. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-3-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
227 lines
7.4 KiB
C
227 lines
7.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_ASM_H__
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#define __RISCV_ASM_H__
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#include <sbi/riscv_encoding.h>
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/* clang-format off */
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#ifdef __ASSEMBLER__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#elif __riscv_xlen == 32
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#define __REG_SEL(a, b) __ASM_STR(b)
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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#define PAGE_SHIFT (12)
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#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE - 1))
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#define REG_L __REG_SEL(ld, lw)
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#define REG_S __REG_SEL(sd, sw)
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#define SZREG __REG_SEL(8, 4)
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#define LGREG __REG_SEL(3, 2)
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#if __SIZEOF_POINTER__ == 8
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#ifdef __ASSEMBLER__
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#define RISCV_PTR .dword
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#define RISCV_SZPTR 8
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#define RISCV_LGPTR 3
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#else
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#define RISCV_PTR ".dword"
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#define RISCV_SZPTR "8"
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#define RISCV_LGPTR "3"
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#endif
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#elif __SIZEOF_POINTER__ == 4
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#ifdef __ASSEMBLER__
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#define RISCV_PTR .word
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#define RISCV_SZPTR 4
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#define RISCV_LGPTR 2
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#else
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#define RISCV_PTR ".word"
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#define RISCV_SZPTR "4"
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#define RISCV_LGPTR "2"
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#endif
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#else
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#error "Unexpected __SIZEOF_POINTER__"
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#endif
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#if (__SIZEOF_INT__ == 4)
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#define RISCV_INT __ASM_STR(.word)
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#define RISCV_SZINT __ASM_STR(4)
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#define RISCV_LGINT __ASM_STR(2)
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#else
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#error "Unexpected __SIZEOF_INT__"
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#endif
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#if (__SIZEOF_SHORT__ == 2)
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#define RISCV_SHORT __ASM_STR(.half)
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#define RISCV_SZSHORT __ASM_STR(2)
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#define RISCV_LGSHORT __ASM_STR(1)
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#else
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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/* clang-format on */
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#ifndef __ASSEMBLER__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \
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: "=r"(__v) \
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: "rK"(__v) \
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: "memory"); \
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__v; \
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})
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__("csrr %0, " __ASM_STR(csr) \
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: "=r"(__v) \
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: \
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: "memory"); \
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__v; \
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})
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/* Variant of csr_read() that allows the compiler to cache the value. */
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#define csr_read_relaxed(csr) \
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({ \
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register unsigned long __v; \
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__asm__ ("csrr %0, " __ASM_STR(csr) : "=r"(__v)); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \
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: \
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: "rK"(__v) \
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: "memory"); \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \
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: "=r"(__v) \
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: "rK"(__v) \
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: "memory"); \
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__v; \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \
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: \
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: "rK"(__v) \
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: "memory"); \
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})
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \
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: "=r"(__v) \
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: "rK"(__v) \
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: "memory"); \
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__v; \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \
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: \
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: "rK"(__v) \
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: "memory"); \
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})
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#if __riscv_xlen == 64
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#define __csrrw64(op, csr, csrh, val) (true ? op(csr, val) : (uint64_t)csrh)
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#define __csrr64( op, csr, csrh) (true ? op(csr) : (uint64_t)csrh)
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#define __csrw64( op, csr, csrh, val) (true ? op(csr, val) : (uint64_t)csrh)
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#elif __riscv_xlen == 32
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#define __csrrw64(op, csr, csrh, val) ( op(csr, val) | (uint64_t)op(csrh, val >> 32) << 32)
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#define __csrr64( op, csr, csrh) ( op(csr) | (uint64_t)op(csrh) << 32)
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#define __csrw64( op, csr, csrh, val) ({ op(csr, val); op(csrh, val >> 32); })
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#endif
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#define csr_swap64( csr, val) __csrrw64(csr_swap, csr, csr ## H, val)
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#define csr_read64( csr) __csrr64 (csr_read, csr, csr ## H)
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#define csr_read_relaxed64(csr) __csrr64 (csr_read_relaxed, csr, csr ## H)
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#define csr_write64( csr, val) __csrw64 (csr_write, csr, csr ## H, val)
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#define csr_read_set64( csr, val) __csrrw64(csr_read_set, csr, csr ## H, val)
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#define csr_set64( csr, val) __csrw64 (csr_set, csr, csr ## H, val)
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#define csr_clear64( csr, val) __csrw64 (csr_clear, csr, csr ## H, val)
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#define csr_read_clear64( csr, val) __csrrw64(csr_read_clear, csr, csr ## H, val)
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#define csr_clear64( csr, val) __csrw64 (csr_clear, csr, csr ## H, val)
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unsigned long csr_read_num(int csr_num);
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void csr_write_num(int csr_num, unsigned long val);
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#define wfi() \
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do { \
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__asm__ __volatile__("wfi" ::: "memory"); \
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} while (0)
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#define ebreak() \
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do { \
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__asm__ __volatile__("ebreak" ::: "memory"); \
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} while (0)
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/* Get current HART id */
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#define current_hartid() ((unsigned int)csr_read_relaxed(CSR_MHARTID))
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/* determine CPU extension, return non-zero support */
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int misa_extension_imp(char ext);
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#define misa_extension(c)\
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({\
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_Static_assert(((c >= 'A') && (c <= 'Z')),\
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"The parameter of misa_extension must be [A-Z]");\
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misa_extension_imp(c);\
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})
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/* Get MXL field of misa, return -1 on error */
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int misa_xlen(void);
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/* Get RISC-V ISA string representation */
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void misa_string(int xlen, char *out, unsigned int out_sz);
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/* Disable pmp entry at a given index */
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int pmp_disable(unsigned int n);
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/* Check if the matching field is set */
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int is_pmp_entry_mapped(unsigned long entry);
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int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
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unsigned long log2len);
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int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
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unsigned long *log2len);
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#endif /* !__ASSEMBLER__ */
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#endif
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