mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 23:41:23 +01:00
7f09fba86e
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
32 lines
788 B
Plaintext
32 lines
788 B
Plaintext
CONFIG_PLATFORM_ALLWINNER_D1=y
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CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_FDT_GPIO=y
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CONFIG_FDT_GPIO_SIFIVE=y
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CONFIG_FDT_I2C=y
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CONFIG_FDT_I2C_SIFIVE=y
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CONFIG_FDT_IPI=y
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CONFIG_FDT_IPI_MSWI=y
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CONFIG_FDT_IRQCHIP=y
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CONFIG_FDT_IRQCHIP_APLIC=y
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CONFIG_FDT_IRQCHIP_IMSIC=y
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CONFIG_FDT_IRQCHIP_PLIC=y
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CONFIG_FDT_RESET=y
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CONFIG_FDT_RESET_GPIO=y
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CONFIG_FDT_RESET_HTIF=y
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CONFIG_FDT_RESET_SIFIVE_TEST=y
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CONFIG_FDT_RESET_SUNXI_WDT=y
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CONFIG_FDT_RESET_THEAD=y
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CONFIG_FDT_SERIAL=y
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CONFIG_FDT_SERIAL_CADENCE=y
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CONFIG_FDT_SERIAL_GAISLER=y
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CONFIG_FDT_SERIAL_HTIF=y
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CONFIG_FDT_SERIAL_SHAKTI=y
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CONFIG_FDT_SERIAL_SIFIVE=y
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CONFIG_FDT_SERIAL_LITEX=y
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CONFIG_FDT_SERIAL_UART8250=y
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CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
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CONFIG_FDT_TIMER=y
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CONFIG_FDT_TIMER_MTIMER=y
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CONFIG_SERIAL_SEMIHOSTING=y
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