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Bo Gan
7bff4e529e
During warm reset, my EIC770X/Hifive Premier P550 can sometimes
encounter memory corruption issue crashing Linux boot. Currently the
issue is mitigated by having a sbi_printf before writing to the reset
register. I analyzed the issue further since then. From the SoC
datasheet[1], it's recommended to implement power-down flow as:
a. Designate a primary core, and let it broadcast requests to other
cores to execute a CEASE insn. Primary core also notifies an
"Externel Agent" to start monitoring.
b. Primary core waits for other cores to CEASE before it CEASEs.
c. "External Agent" waits for primary core to CEASE before resets
the Core Complex.
It's possible that EIC770X can trigger undefined behavior if the core
complex is reset while the harts are actively running. The sbi_printf
in the reset handler effectively hides the problem by delaying the
reset -- by the time sbi_printf finishes, all other harts will have
already landed in the loop in sbi_hsm_hart_wait(), which parks the hart.
Without the sbi_printf, I confirmed that other harts haven't reached
sbi_hsm_hart_wait yet before current hart resets the SoC. (by debugging)
To safely reset, and inspired by the datasheet, the warm reset logic
in eic770x.c now use the current hart as both primary core and the
"External Agent", and other harts as secondary cores. It leverages
the HSM framework and a new eic770x_hsm device to CEASE other harts,
and wait for them to CEASE before resets the SoC. with the sbi_printf
before reset removed, and this logic in place, stress test shows that
the memory corruption issue no longer occurs.
The new eic770x_hsm device is only used for the reset-CEASE logic at
the moment, and may be extended to a fully functional HSM device in
the future.
[1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual
Fixes: e5797e0688 ("platform: generic: eswin: add EIC7700")
Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260605075708.96-3-ganboing@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
112 lines
3.9 KiB
C
112 lines
3.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Bo Gan <ganboing@gmail.com>
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*
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*/
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#ifndef __EIC770X_H__
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#define __EIC770X_H__
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#include <sbi/riscv_asm.h>
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struct eic770x_board_override {
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struct sbi_system_reset_device *reset_dev;
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};
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void eic770x_cease_other_harts(void);
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/* CSRs */
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#define EIC770X_CSR_BRPREDICT 0x7c0
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#define EIC770X_CSR_FEAT0 0x7c1
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#define EIC770X_CSR_FEAT1 0x7c2
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#define EIC770X_CSR_L1_HWPF 0x7c3
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#define EIC770X_CSR_L2_HWPF 0x7c4
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/* Hart ID to core/die conversion */
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#define CPU_CORE_BITS 2
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#define CPU_CORE_MASK ((1 << CPU_CORE_BITS) - 1)
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#define CPU_DIE_SHIFT CPU_CORE_BITS
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#define CPU_DIE_BITS 1
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#define CPU_DIE_MASK ((1 << CPU_DIE_BITS) - 1)
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#define hart_core(i) ((i) & CPU_CORE_MASK)
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#define hart_die(i) (((i) >> CPU_DIE_SHIFT) & CPU_DIE_MASK)
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#define current_hart_core() hart_core(current_hartid())
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#define current_hart_die() hart_die(current_hartid())
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/* P550 Internal and System Port 0 */
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#define EIC770X_P550INT_SIZE 0x20000000UL
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#define EIC770X_P550INT_BASE(d) (0UL + EIC770X_P550INT_SIZE * (d))
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#define EIC770X_P550INT_LOCAL EIC770X_P550INT_BASE(current_hart_die())
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#define EIC770X_TL64D2D_OUT (EIC770X_P550INT_LOCAL + 0x200000)
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#define EIC770X_TL256D2D_OUT (EIC770X_P550INT_LOCAL + 0x202000)
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#define EIC770X_TL256D2D_IN (EIC770X_P550INT_LOCAL + 0x204000)
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#define EIC770X_L3_ZERO_SIZE 0x400000UL
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#define EIC770X_L3_ZERO_BASE(d) (EIC770X_P550INT_BASE(d) + 0x1a000000)
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#define EIC770X_L3_ZERO_LOCAL EIC770X_L3_ZERO_BASE(current_hart_die())
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#define EIC770X_L3_ZERO_REMOTE EIC770X_L3_ZERO_BASE(1 - current_hart_die())
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#define EIC770X_SYSPORT_SIZE 0x20000000UL
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#define EIC770X_SYSPORT_BASE(d) (0x40000000UL + EIC770X_SYSPORT_SIZE * (d))
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#define EIC770X_SYSPORT_LOCAL EIC770X_SYSPORT_BASE(current_hart_die())
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#define EIC770X_UART0 (EIC770X_SYSPORT_LOCAL + 0x10900000UL)
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#define EIC770X_UART_SIZE 0x10000UL
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#define EIC770X_UART(x) (EIC770X_UART0 + EIC770X_UART_SIZE * (x))
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#define EIC770X_UART_REG_SHIFT 2
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#define EIC770X_UART_REG_WIDTH 4
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#define EIC770X_SYSCON(d) (EIC770X_SYSPORT_BASE(d) + 0x11810000UL)
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#define EIC770X_MCPU_STATUS(d) (EIC770X_SYSCON(d) + 0x608UL)
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#define EIC770X_MC_CEASE_BIT(c) (1UL << (15 - c))
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#define EIC770X_SYSCRG(d) (EIC770X_SYSPORT_BASE(d) + 0x11828000UL)
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#define EIC770X_SYSCRG_LOCAL (EIC770X_SYSPORT_LOCAL + 0x11828000UL)
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#define EIC770X_SYSCRG_LSPCLK0 (EIC770X_SYSCRG_LOCAL + 0x200UL)
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#define EIC770X_SYSCRG_MCCLK(d) (EIC770X_SYSCRG(d) + 0x208UL)
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#define EIC770X_SYSCRG_SYSCLK (EIC770X_SYSCRG_LOCAL + 0x20cUL)
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#define EIC770X_SYSCRG_SYSRST (EIC770X_SYSCRG_LOCAL + 0x300UL)
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/* Memory Ports */
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#define EIC770X_MEMPORT_BASE 0x0080000000UL // 2G
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#define EIC770X_MEMPORT_SIZE 0x7f80000000UL // +510G
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#define EIC770X_MEMPORT_LIMIT (EIC770X_MEMPORT_BASE + EIC770X_MEMPORT_SIZE)
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#define EIC770X_D0_MEM_BASE 0x0080000000UL // 2G
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#define EIC770X_D0_MEM_SIZE 0x0f80000000UL // +62G
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#define EIC770X_D0_MEM_LIMIT (EIC770X_D0_MEM_BASE + EIC770X_D0_MEM_SIZE)
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#define EIC770X_D1_MEM_BASE 0x2000000000UL // 128G
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#define EIC770X_D1_MEM_SIZE 0x1000000000UL // +64G
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#define EIC770X_D1_MEM_LIMIT (EIC770X_D1_MEM_BASE + EIC770X_D1_MEM_SIZE)
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#define EIC770X_CACHED_BASE (current_hart_die() ? \
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EIC770X_D1_MEM_BASE : \
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EIC770X_D0_MEM_BASE)
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/* Uncached memory mapped in System Port 1 */
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#define EIC770X_D0_UC_BASE 0xc000000000UL
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#define EIC770X_D1_UC_BASE 0xe000000000UL
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#define EIC770X_UNCACHED_BASE (current_hart_die() ? \
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EIC770X_D1_UC_BASE : \
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EIC770X_D0_UC_BASE)
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#define EIC770X_TO_UNCACHED(x) ((x) - EIC770X_CACHED_BASE + \
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EIC770X_UNCACHED_BASE)
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/* Clock definitions */
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#define EIC770X_XTAL_CLK_RATE 24000000UL
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#define EIC770X_SPLL0_OUT1_RATE 1600000000UL
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#define EIC770X_SPLL0_OUT2_RATE 800000000UL
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#define EIC770X_SPLL0_OUT3_RATE 400000000UL
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#define EIC770X_UART_CLK_BIT(x) (1UL << ((x) + 17))
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#define EIC770X_SYSCLK_SEL(x) ((x) & 1)
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#define EIC770X_SYSCLK_DIV(x) \
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({ \
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uint32_t divisor = ((x) >> 4) & 7; \
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divisor > 2 ? divisor : 2; \
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})
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/* Reset definitions */
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#define EIC770X_SYSRST_VAL 0x1AC0FFE6UL
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#endif
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