mirror of
https://github.com/riscv-software-src/opensbi.git
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79dfc3a868
Refactor MIPS P8700 support, convert P8700 into a "CPU" and add 2 platforms using this CPU: - "boston" - FPGA platform developed by MIPS - "eyeq7h" - automotive platform by Mobileye Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-10-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <mips/p8700.h>
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#include <mips/mips-cm.h>
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const struct p8700_cm_info *p8700_cm_info;
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void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
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unsigned long prot, unsigned long addr,
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unsigned long log2len)
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{
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int pmacfg_csr, pmacfg_shift;
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unsigned long cfgmask;
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unsigned long pmacfg, cca;
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pmacfg_csr = (CSR_MIPSPMACFG0 + (n >> 2)) & ~1;
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pmacfg_shift = (n & 7) << 3;
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cfgmask = ~(0xffUL << pmacfg_shift);
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/* Read pmacfg to change cacheability */
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pmacfg = (csr_read_num(pmacfg_csr) & cfgmask);
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cca = (flags & SBI_DOMAIN_MEMREGION_MMIO) ? CCA_CACHE_DISABLE :
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CCA_CACHE_ENABLE | PMA_SPECULATION;
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pmacfg |= ((cca << pmacfg_shift) & ~cfgmask);
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csr_write_num(pmacfg_csr, pmacfg);
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}
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void mips_p8700_power_up_other_cluster(u32 hartid)
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{
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unsigned int cl = cpu_cluster(hartid);
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/* Power up CM in cluster */
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write_cpc_pwrup_ctl(hartid, 1);
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/* Wait for the CM to start up */
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for (int i = 100; i > 0; i--) {
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u32 stat = read_cpc_cm_stat_conf(hartid);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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if (stat == CPC_Cx_STAT_CONF_SEQ_STATE_U5)
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return;
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cpu_relax();
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}
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sbi_printf("ERROR: Fail to power up cluster %u\n", cl);
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}
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extern void mips_warm_boot(void);
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struct mips_boot_params {
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u32 hartid;
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u32 target_state;
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};
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static bool mips_hart_reached_state(void *arg)
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{
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struct mips_boot_params *p = arg;
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u32 stat = read_cpc_co_stat_conf(p->hartid);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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return stat == p->target_state;
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}
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int mips_p8700_hart_start(u32 hartid, ulong saddr)
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{
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to start. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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/* Change reset base to mips_warm_boot */
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write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot);
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if (cpu_hart(hartid) == 0) {
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unsigned int const timeout_ms = 10;
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bool booted;
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struct mips_boot_params p = {
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.hartid = hartid,
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.target_state = CPC_Cx_STAT_CONF_SEQ_STATE_U6,
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};
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/* Ensure its coherency is disabled */
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write_gcr_co_coherence(hartid, 0);
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/* Start cluster cl core co hart 0 */
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid));
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/* Reset cluster cl core co hart 0 */
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write_cpc_co_cmd(hartid, CPC_Cx_CMD_RESET);
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booted = sbi_timer_waitms_until(mips_hart_reached_state, &p, timeout_ms);
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if (!booted) {
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sbi_printf("ERROR: failed to boot hart 0x%x in %d ms\n",
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hartid, timeout_ms);
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return -SBI_ETIMEDOUT;
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}
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} else {
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid));
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}
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return 0;
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}
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int mips_p8700_hart_stop()
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{
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u32 hartid = current_hartid();
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to stop. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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write_cpc_co_vp_stop(hartid, 1 << cpu_hart(hartid));
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return 0;
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}
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int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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const struct p8700_cm_info *data = match->data;
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if (!data) {
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sbi_printf("Missing CM info for %s\n", match->compatible);
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return SBI_EINVAL;
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}
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p8700_cm_info = data;
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return SBI_OK;
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}
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