mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-07-26 15:51:38 +01:00
Pawandeep OzaandAnup Patel
759910326c
Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep <pawandeep.oza@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
172 lines
5.5 KiB
C
172 lines
5.5 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#ifndef __SBI_IRQCHIP_H__
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#define __SBI_IRQCHIP_H__
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_types.h>
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struct sbi_scratch;
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/** irqchip message signalled interrupt (MSI) */
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struct sbi_irqchip_msi_msg {
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u32 address_lo;
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u32 address_hi;
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u32 data;
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};
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/** irqchip hardware device */
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struct sbi_irqchip_device {
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/** Node in the list of irqchip devices (private) */
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struct sbi_dlist node;
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/** Internal data of all hardware interrupts of this irqchip (private) */
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struct sbi_irqchip_hwirq_data *hwirqs;
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/** List of interrupt handlers (private) */
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struct sbi_dlist handler_list;
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/** Unique ID of this irqchip */
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u32 id;
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/** Capabilities of this irqchip */
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#define SBI_IRQCHIP_CAPS_WIRED BIT(0)
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#define SBI_IRQCHIP_CAPS_MSI BIT(1)
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unsigned long caps;
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/** Number of hardware IRQs of this irqchip */
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u32 num_hwirq;
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/** Set of harts targetted by this irqchip */
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struct sbi_hartmask target_harts;
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/** Initialize per-hart state for the current hart */
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int (*warm_init)(struct sbi_irqchip_device *chip);
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/** Process hardware interrupts from this irqchip */
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int (*process_hwirqs)(struct sbi_irqchip_device *chip);
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/** Setup a hardware interrupt of this irqchip */
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int (*hwirq_setup)(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 hwirq_flags);
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#define SBI_HWIRQ_FLAGS_NONE 0x00000000UL
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#define SBI_HWIRQ_FLAGS_EDGE_RISING 0x00000001UL
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#define SBI_HWIRQ_FLAGS_EDGE_FALLING 0x00000002UL
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#define SBI_HWIRQ_FLAGS_EDGE_BOTH (SBI_HWIRQ_FLAGS_EDGE_RISING | \
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SBI_HWIRQ_FLAGS_EDGE_FALLING)
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#define SBI_HWIRQ_FLAGS_LEVEL_HIGH 0x00000004UL
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#define SBI_HWIRQ_FLAGS_LEVEL_LOW 0x00000008UL
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#define SBI_HWIRQ_FLAGS_LEVEL_SENSE_MASK 0x0000000fUL
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/** Cleanup a hardware interrupt of this irqchip */
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void (*hwirq_cleanup)(struct sbi_irqchip_device *chip, u32 hwirq);
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/** End of hardware interrupt of this irqchip */
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void (*hwirq_eoi)(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Set hardware interrupt affinity */
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int (*hwirq_set_affinity)(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 hart_index);
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/** Mask a hardware interrupt of this irqchip */
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void (*hwirq_mask)(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Unmask a hardware interrupt of this irqchip */
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void (*hwirq_unmask)(struct sbi_irqchip_device *chip, u32 hwirq);
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};
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/**
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* Process external interrupts
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*
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* This function is called by sbi_trap_handler() to handle external
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* interrupts.
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*
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* @param regs pointer for trap registers
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*/
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int sbi_irqchip_process(void);
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/**
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* Process a hwirq of an irqchip device
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*
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* This function is called by irqchip drivers to handle hardware
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* interrupts of the irqchip.
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*/
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int sbi_irqchip_process_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Unmask a hardware interrupt */
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int sbi_irqchip_unmask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Mask a hardware interrupt */
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int sbi_irqchip_mask_hwirq(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Helper to set private data in sbi_irqchip_hwirq_data */
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int sbi_irqchip_set_hwirq_priv(struct sbi_irqchip_device *chip, u32 hwirq, void *priv);
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/** Helper to retrieve data from sbi_irqchip_hwirq_data */
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void *sbi_irqchip_get_hwirq_priv(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Default raw hardware interrupt handler */
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int sbi_irqchip_raw_handler_default(struct sbi_irqchip_device *chip, u32 hwirq);
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/** Set raw hardware interrupt handler */
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int sbi_irqchip_set_raw_handler(struct sbi_irqchip_device *chip, u32 hwirq,
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int (*raw_hndl)(struct sbi_irqchip_device *, u32));
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/** Get hardware interrupt affinity */
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int sbi_irqchip_get_affinity(struct sbi_irqchip_device *chip, u32 hwirq,
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u32 *out_hart_index);
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/** Set hardware interrupt affinity */
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int sbi_irqchip_set_affinity(struct sbi_irqchip_device *chip, u32 hwirq, u32 hart_index);
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/** Write MSI message to the hardware interrupt handler */
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int sbi_irqchip_write_msi(struct sbi_irqchip_device *chip, u32 hwirq,
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const struct sbi_irqchip_msi_msg *msg);
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/** Register a hardware MSI handler */
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int sbi_irqchip_register_msi(struct sbi_irqchip_device *chip, u32 num_hwirq,
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void (*write_msi)(u32 hwirq,
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const struct sbi_irqchip_msi_msg *msg,
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void *priv),
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int (*callback)(u32 hwirq, void *priv), void *priv,
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u32 *out_first_hwirq);
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/** Register a hardware interrupt handler */
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int sbi_irqchip_register_handler(struct sbi_irqchip_device *chip,
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u32 first_hwirq, u32 num_hwirq, u32 hwirq_flags,
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int (*callback)(u32 hwirq, void *priv), void *priv);
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/** Register a hardware interrupts as reserved */
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int sbi_irqchip_register_reserved(struct sbi_irqchip_device *chip,
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u32 first_hwirq, u32 num_hwirq);
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/** Unregister a hardware interrupt handler */
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int sbi_irqchip_unregister_handler(struct sbi_irqchip_device *chip,
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u32 first_hwirq, u32 num_hwirq);
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/** Find an irqchip device based on matching capabilities */
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struct sbi_irqchip_device *sbi_irqchip_find_device_by_caps(unsigned long caps,
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struct sbi_irqchip_device *first);
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/** Find an irqchip device based on unique ID */
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struct sbi_irqchip_device *sbi_irqchip_find_device(u32 id);
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/** Register an irqchip device to receive callbacks */
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int sbi_irqchip_add_device(struct sbi_irqchip_device *chip);
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/** Initialize interrupt controllers */
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int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot);
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/** Exit interrupt controllers */
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void sbi_irqchip_exit(struct sbi_scratch *scratch);
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#endif
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