mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-06-12 22:31:45 +01:00
73bc794b40
When switching between domains with different satp.MODE values (e.g. Sv39 to Sv48), the RISC-V ISA permits hardware to use cached translations from the old virtual-address width if no SFENCE.VMA intervenes. This constrained-unpredictable behavior is clarified in riscv-isa-manual PR #2219. The hart protection re-configuration will anyway do full SFENCE / HFENCE so move the hart protection re-configuration after register context switch in switch_to_next_domain_context() to ensure translations from the new domain's address width are used. Link: https://github.com/riscv/riscv-isa-manual/pull/2219 Signed-off-by: Zishun Yi <vulab@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260429181747.160033-1-vulab@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>