mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-12-22 06:12:02 +00:00
e5797e0688
Initial platform support for ESWIN Computing EIC7700 based on public SoC
datasheet[1] and tested on HiFive Premier P550. Vendor U-boot/Linux boots
fine, and I've tested Geekbench 6.5.0 Preview and got scores on par with
the vendor OpenSBI. System shutdown/reboot for HiFive Premier P550 and
other boards will be implemented in subsequent commits. At this point,
only SoC-level warm reset is implemented.
The files and functions are intentionally named as eic770x in many places
for future enhancements to support the 2 die version of the same SoC,
namely EIC7702, seen on DC-ROMA AI PC FML13V03 [2]. This patch set only
deals with the single die version, and the assumption is we can be either
die with id=0 or id=1, but there's only a single die in the system, or we
are only using a single die out of 2. However, the way the SoC handles 2-
die greatly affects how we configure it in a 1-die setup. EIC770X address
map has die 0/1 memory regions interleaved (see comments in eic770x.c).
If only 1 die is connected or active, it creates holes in the address map
for those regions corresponding to the remote die. When speculative-
execution or HW prefetcher touches data-cacheable regions that happen to
fall into those holes, it can trigger bus error. Specifically:
- Remote (non-existent) die L3 zero device
- Remote (non-existent) die cached memory region
- Other holes in Memory Port
To make matters worse, EIC770X doesn't have cache coherent DMA, and due
to the fact that the P550 core lacks Svpbmt, the SoC maps main memory
twice as different regions, so it can bypass cache and fetch the data
directly from memory. In address space, we have two memory regions, one
as cached, the other as uncached. Thus, we also need an extra PMP entry
to protect OpenSBI blob from the uncached window. To do this, platform
code requires single_fw_region, otherwise, we'll run out of PMP entries.
EIC770X also have several feature disable/enable CSRs accessible in M
mode. By default many core features such as speculation and HW prefetch
are disabled, and M mode software is responsible of enabling. Hence,
introduce 4 new build time tunable parameters to Kconfig, which reflects
the values get updated to those CSRs:
- ESWIN_EIC770X_FEAT0_CFG
- ESWIN_EIC770X_FEAT1_CFG
- ESWIN_EIC770X_L1_HWPF_CFG
- ESWIN_EIC770X_L2_HWPF_CFG
The default values are somewhat optimal for generic workloads. They are
dumped when running SiFive's vendor OpenSBI, and in addition, with my
own tuning to address the perf regression reported by drmpeg [3]
To build the firmware+u-boot blob, Use the following, and docs [4] for
testing it with UART boot without flashing:
make FW_TEXT_START=0x80000000 \
FW_PAYLOAD_OFFSET=0x200000 \
FW_PAYLOAD_PATH=u-boot-nodtb.bin \
FW_PAYLOAD_FDT_ADDR=0xf8000000 \
FW_FDT_PATH=u-boot.dtb
[1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual
[2] https://github.com/geerlingguy/sbc-reviews/issues/82
[3] https://forums.sifive.com/t/low-1-core-stream-bandwidth/7274/15
[4] https://github.com/ganboing/EIC770x-Docs/blob/main/p550/bootchain/UART-Boot.md
Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251218104243.562667-6-ganboing@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
109 lines
2.0 KiB
Plaintext
109 lines
2.0 KiB
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
|
|
|
|
config PLATFORM_GENERIC
|
|
bool
|
|
select FDT
|
|
select FDT_DOMAIN
|
|
select FDT_PMU
|
|
default y
|
|
|
|
if PLATFORM_GENERIC
|
|
|
|
config PLATFORM_GENERIC_NAME
|
|
string "Platform default name"
|
|
default "Generic"
|
|
|
|
config PLATFORM_GENERIC_MAJOR_VER
|
|
int "Platform major version"
|
|
range 0 65535
|
|
default 0
|
|
|
|
config PLATFORM_GENERIC_MINOR_VER
|
|
int "Platform minor version"
|
|
range 0 65535
|
|
default 1
|
|
|
|
config PLATFORM_GENERIC_FDT_EMPTY_SPACE
|
|
int "Platform FDT empty space (KB)"
|
|
range 0 1024
|
|
default 4
|
|
|
|
config PLATFORM_ALLWINNER_D1
|
|
bool "Allwinner D1 support"
|
|
depends on FDT_IRQCHIP_PLIC
|
|
select THEAD_C9XX_PMU
|
|
default n
|
|
|
|
config PLATFORM_ANDES_AE350
|
|
bool "Andes AE350 support"
|
|
select SYS_ATCSMU
|
|
select ANDES_PMU
|
|
select ANDES_PMA
|
|
default n
|
|
|
|
config PLATFORM_ANDES_QILAI
|
|
bool "Andes QiLai support"
|
|
select ANDES_PMU
|
|
select ANDES_PMA
|
|
select ANDES_SBI
|
|
default n
|
|
|
|
config PLATFORM_ESWIN_EIC770X
|
|
bool "ESWIN EIC770X support"
|
|
default n
|
|
|
|
config PLATFORM_OPENHWGROUP_OPENPITON
|
|
bool "OpenHWGroup Openpiton support"
|
|
default n
|
|
|
|
config PLATFORM_OPENHWGROUP_ARIANE
|
|
bool "OpenHWGroup Ariane support"
|
|
default n
|
|
|
|
config PLATFORM_RENESAS_RZFIVE
|
|
bool "Renesas RZ/Five support"
|
|
select ANDES_PMA
|
|
select ANDES_SBI
|
|
select ANDES_PMU
|
|
default n
|
|
|
|
config PLATFORM_SIFIVE_FU540
|
|
bool "SiFive FU540 support"
|
|
default n
|
|
|
|
config PLATFORM_SIFIVE_FU740
|
|
bool "SiFive FU740 support"
|
|
depends on FDT_RESET && FDT_I2C
|
|
default n
|
|
|
|
config PLATFORM_SOPHGO_SG2042
|
|
bool "Sophgo sg2042 support"
|
|
select THEAD_C9XX_ERRATA
|
|
select THEAD_C9XX_PMU
|
|
default n
|
|
|
|
config PLATFORM_STARFIVE_JH7110
|
|
bool "StarFive JH7110 support"
|
|
default n
|
|
|
|
config PLATFORM_THEAD
|
|
bool "THEAD C9xx support"
|
|
select THEAD_C9XX_ERRATA
|
|
select THEAD_C9XX_PMU
|
|
default n
|
|
|
|
config PLATFORM_MIPS_P8700
|
|
bool "MIPS P8700 support"
|
|
default n
|
|
|
|
config PLATFORM_SPACEMIT_K1
|
|
bool "Spacemit K1 support"
|
|
select FDT_HSM_SPACEMIT
|
|
default n
|
|
|
|
source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
|
|
source "$(OPENSBI_SRC_DIR)/platform/generic/eswin/Kconfig"
|
|
source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
|
|
|
|
endif
|