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dcdaf30274
This patch generalizes the logic to add a memory range with desired alignment and flags of consecutive regions to the root domain. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __TIMER_ACLINT_MTIMER_H__
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#define __TIMER_ACLINT_MTIMER_H__
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#include <sbi/sbi_types.h>
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#define ACLINT_MTIMER_ALIGN 0x8
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#define ACLINT_MTIMER_MAX_HARTS 4095
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#define ACLINT_DEFAULT_MTIME_OFFSET 0x7ff8
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#define ACLINT_DEFAULT_MTIME_SIZE 0x8
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#define ACLINT_DEFAULT_MTIMECMP_OFFSET 0x0000
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#define ACLINT_DEFAULT_MTIMECMP_SIZE 0x7ff8
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#define CLINT_MTIMER_OFFSET 0x4000
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#define MTIMER_REGION_ALIGN 0x1000
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struct aclint_mtimer_data {
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/* Public details */
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unsigned long mtime_freq;
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unsigned long mtime_addr;
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unsigned long mtime_size;
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unsigned long mtimecmp_addr;
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unsigned long mtimecmp_size;
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u32 first_hartid;
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u32 hart_count;
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bool has_64bit_mmio;
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bool has_shared_mtime;
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/* Private details (initialized and used by ACLINT MTIMER library) */
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struct aclint_mtimer_data *time_delta_reference;
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unsigned long time_delta_computed;
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u64 (*time_rd)(volatile u64 *addr);
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void (*time_wr)(bool timecmp, u64 value, volatile u64 *addr);
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};
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void aclint_mtimer_sync(struct aclint_mtimer_data *mt);
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void aclint_mtimer_set_reference(struct aclint_mtimer_data *mt,
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struct aclint_mtimer_data *ref);
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int aclint_mtimer_warm_init(void);
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int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
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struct aclint_mtimer_data *reference);
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#endif
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