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https://github.com/riscv-software-src/opensbi.git
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66ab965e54
Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#include <platform_override.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <mips/p8700.h>
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#include <mips/mips-cm.h>
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#if CLUSTERS_IN_PLATFORM > 1
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static void power_up_other_cluster(u32 hartid)
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{
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unsigned int stat;
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unsigned int timeout;
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bool local_p = (cpu_cluster(current_hartid()) == cpu_cluster(hartid));
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/* Power up cluster cl core 0 hart 0 */
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write_cpc_pwrup_ctl(hartid, 1, local_p);
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/* Wait for the CM to start up */
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timeout = 100;
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while (true) {
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stat = read_cpc_cm_stat_conf(hartid, local_p);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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if (stat == CPC_Cx_STAT_CONF_SEQ_STATE_U5)
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break;
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/* Delay a little while before we start warning */
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if (timeout) {
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sbi_dprintf("Delay a little while before we start warning\n");
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timeout--;
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}
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else {
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sbi_printf("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n",
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cpu_cluster(hartid), stat);
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break;
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}
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}
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}
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#endif
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static int mips_hart_start(u32 hartid, ulong saddr)
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{
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unsigned int stat;
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unsigned int timeout;
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bool local_p = (cpu_cluster(current_hartid()) == cpu_cluster(hartid));
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to start. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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if (cpu_hart(hartid) == 0) {
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/* Ensure its coherency is disabled */
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write_gcr_co_coherence(hartid, 0, local_p);
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/* Start cluster cl core co hart 0 */
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid), local_p);
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/* Reset cluster cl core co hart 0 */
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write_cpc_co_cmd(hartid, CPC_Cx_CMD_RESET, local_p);
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timeout = 100;
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while (true) {
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stat = read_cpc_co_stat_conf(hartid, local_p);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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if (stat == CPC_Cx_STAT_CONF_SEQ_STATE_U6)
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break;
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/* Delay a little while before we start warning */
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if (timeout) {
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sbi_timer_mdelay(10);
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timeout--;
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}
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else {
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sbi_printf("Waiting for cluster %u core %u hart %u to start... STAT_CONF=0x%x\n",
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cpu_cluster(hartid),
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cpu_core(hartid), cpu_hart(hartid),
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stat);
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break;
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}
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}
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}
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else {
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid), local_p);
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}
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return 0;
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}
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static int mips_hart_stop()
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{
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u32 hartid = current_hartid();
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bool local_p = (cpu_cluster(current_hartid()) == cpu_cluster(hartid));
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to stop. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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write_cpc_co_vp_stop(hartid, 1 << cpu_hart(hartid), local_p);
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return 0;
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}
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static const struct sbi_hsm_device mips_hsm = {
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.name = "mips_hsm",
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.hart_start = mips_hart_start,
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.hart_stop = mips_hart_stop,
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};
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static int mips_p8700_final_init(bool cold_boot)
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{
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if (cold_boot)
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sbi_hsm_set_device(&mips_hsm);
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return generic_final_init(cold_boot);
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}
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static int mips_p8700_early_init(bool cold_boot)
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{
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int rc;
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rc = generic_early_init(cold_boot);
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if (rc)
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return rc;
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if (cold_boot) {
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#if CLUSTERS_IN_PLATFORM > 1
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int i;
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/* Power up other clusters in the platform. */
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for (i = 1; i < CLUSTERS_IN_PLATFORM; i++) {
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power_up_other_cluster(i << NEW_CLUSTER_SHIFT);
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}
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#endif
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/* For the CPC mtime region, the minimum size is 0x10000. */
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rc = sbi_domain_root_add_memrange(CM_BASE, SIZE_FOR_CPC_MTIME,
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P8700_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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/* For the APLIC and ACLINT m-mode region */
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rc = sbi_domain_root_add_memrange(AIA_BASE, SIZE_FOR_AIA_M_MODE,
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P8700_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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#if CLUSTERS_IN_PLATFORM > 1
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for (i = 0; i < CLUSTERS_IN_PLATFORM; i++) {
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/* For the CPC mtime region, the minimum size is 0x10000. */
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rc = sbi_domain_root_add_memrange(GLOBAL_CM_BASE[i], SIZE_FOR_CPC_MTIME,
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P8700_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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/* For the APLIC and ACLINT m-mode region */
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rc = sbi_domain_root_add_memrange(AIA_BASE - CM_BASE + GLOBAL_CM_BASE[i], SIZE_FOR_AIA_M_MODE,
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P8700_ALIGN,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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}
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#endif
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}
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return 0;
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}
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static int mips_p8700_nascent_init(void)
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{
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u64 hartid = current_hartid();
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u64 cm_base = CM_BASE;
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int i;
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/* Coherence enable for every core */
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if (cpu_hart(hartid) == 0) {
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cm_base += (cpu_core(hartid) << CM_BASE_CORE_SHIFT);
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__raw_writeq(GCR_CORE_COH_EN_EN,
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(void *)(cm_base + GCR_OFF_LOCAL +
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GCR_CORE_COH_EN));
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mb();
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}
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/* Set up pmp for DRAM */
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csr_write(CSR_PMPADDR14, DRAM_PMP_ADDR);
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/* All from 0x0 */
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csr_write(CSR_PMPADDR15, 0x1fffffffffffffff);
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csr_write(CSR_PMPCFG2, ((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<56)|
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((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<48));
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/* Set cacheable for pmp6, uncacheable for pmp7 */
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csr_write(CSR_MIPSPMACFG2, ((u64)CCA_CACHE_DISABLE << 56)|
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((u64)CCA_CACHE_ENABLE << 48));
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/* Reset pmpcfg0 */
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csr_write(CSR_PMPCFG0, 0);
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/* Reset pmacfg0 */
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csr_write(CSR_MIPSPMACFG0, 0);
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mb();
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/* Per cluster set up */
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if (cpu_core(hartid) == 0 && cpu_hart(hartid) == 0) {
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/* Enable L2 prefetch */
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__raw_writel(0xfffff110,
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(void *)(cm_base + L2_PFT_CONTROL_OFFSET));
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__raw_writel(0x15ff,
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(void *)(cm_base + L2_PFT_CONTROL_B_OFFSET));
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}
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/* Per core set up */
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if (cpu_hart(hartid) == 0) {
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/* Enable load pair, store pair, and HTW */
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csr_clear(CSR_MIPSCONFIG7, (1<<12)|(1<<13)|(1<<7));
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/* Disable noRFO, misaligned load/store */
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csr_set(CSR_MIPSCONFIG7, (1<<25)|(1<<9));
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/* Enable L1-D$ Prefetch */
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csr_write(CSR_MIPSCONFIG11, 0xff);
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for (i = 0; i < 8; i++) {
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csr_set(CSR_MIPSCONFIG8, 4 + 0x100 * i);
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csr_set(CSR_MIPSCONFIG9, 8);
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mb();
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RISCV_FENCE_I;
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}
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}
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/* Per hart set up */
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/* Enable AMO and RDTIME illegal instruction exceptions. */
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csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
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return 0;
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}
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static int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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generic_platform_ops.early_init = mips_p8700_early_init;
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generic_platform_ops.final_init = mips_p8700_final_init;
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generic_platform_ops.nascent_init = mips_p8700_nascent_init;
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return 0;
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}
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static const struct fdt_match mips_p8700_match[] = {
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{ .compatible = "mips,p8700" },
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{ },
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};
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const struct fdt_driver mips_p8700 = {
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.match_table = mips_p8700_match,
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.init = mips_p8700_platform_init,
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};
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