Mirrors/opensbi
3
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2026-06-12 22:31:45 +01:00
Code Issues Packages Projects Releases Wiki Activity
Files
63350c6ea6a9ba8097b15c7159a00c428377623c
opensbi/lib/sbi/riscv_asm.c
T
Nicholas Piggin 63350c6ea6 lib: sbi: Add hart_ prefix to PMP functions 
PMP functions that deal with hart PMP CSRs are given a sbi_hart_ prefix,
to distinguish from RISC-V PMP encoding functions.

The is_pmp_entry_mapped() function is changed a little more, to align
with other PMP conventions, and made to return a bool to make it more
obvious that it returns a bool and not an SBI_ return code.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260430045528.420437-8-npiggin@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-10 17:37:49 +05:30

384 lines
11 KiB
C
Raw Blame History

/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_encoding.h>
#include <sbi/sbi_error.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_console.h>
#include <sbi/sbi_pmp.h>
/* determine CPU extension, return non-zero support */
int misa_extension_imp(char ext)
{
unsigned long misa = csr_read(CSR_MISA);
if (misa) {
if ('A' <= ext && ext <= 'Z')
return misa & (1 << (ext - 'A'));
if ('a' <= ext && ext <= 'z')
return misa & (1 << (ext - 'a'));
return 0;
}
return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
}
int misa_xlen(void)
{
long r;
if (csr_read(CSR_MISA) == 0)
return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
__asm__ __volatile__(
"csrr t0, misa\n\t"
"slti t1, t0, 0\n\t"
"slli t1, t1, 1\n\t"
"slli t0, t0, 1\n\t"
"slti t0, t0, 0\n\t"
"add %0, t0, t1"
: "=r"(r)
:
: "t0", "t1");
return r ? r : -1;
}
void misa_string(int xlen, char *out, unsigned int out_sz)
{
unsigned int i, pos = 0;
const char valid_isa_order[] = "iemafdqclbjtpvnhkorwxyzg";
if (!out)
return;
if (5 <= (out_sz - pos)) {
out[pos++] = 'r';
out[pos++] = 'v';
switch (xlen) {
case 1:
out[pos++] = '3';
out[pos++] = '2';
break;
case 2:
out[pos++] = '6';
out[pos++] = '4';
break;
case 3:
out[pos++] = '1';
out[pos++] = '2';
out[pos++] = '8';
break;
default:
sbi_panic("%s: Unknown misa.MXL encoding %d",
__func__, xlen);
return;
}
}
for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
if (misa_extension_imp(valid_isa_order[i]))
out[pos++] = valid_isa_order[i];
}
if (pos < out_sz)
out[pos++] = '\0';
}
unsigned long csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num) \
case __csr_num: \
return csr_read(__csr_num);
#define switchcase_csr_read_2(__csr_num) \
switchcase_csr_read(__csr_num + 0) \
switchcase_csr_read(__csr_num + 1)
#define switchcase_csr_read_4(__csr_num) \
switchcase_csr_read_2(__csr_num + 0) \
switchcase_csr_read_2(__csr_num + 2)
#define switchcase_csr_read_8(__csr_num) \
switchcase_csr_read_4(__csr_num + 0) \
switchcase_csr_read_4(__csr_num + 4)
#define switchcase_csr_read_16(__csr_num) \
switchcase_csr_read_8(__csr_num + 0) \
switchcase_csr_read_8(__csr_num + 8)
#define switchcase_csr_read_32(__csr_num) \
switchcase_csr_read_16(__csr_num + 0) \
switchcase_csr_read_16(__csr_num + 16)
#define switchcase_csr_read_64(__csr_num) \
switchcase_csr_read_32(__csr_num + 0) \
switchcase_csr_read_32(__csr_num + 32)
#define switchcase_csr_read_128(__csr_num) \
switchcase_csr_read_64(__csr_num + 0) \
switchcase_csr_read_64(__csr_num + 64)
#define switchcase_csr_read_256(__csr_num) \
switchcase_csr_read_128(__csr_num + 0) \
switchcase_csr_read_128(__csr_num + 128)
switch (csr_num) {
switchcase_csr_read_16(CSR_PMPCFG0)
switchcase_csr_read_64(CSR_PMPADDR0)
switchcase_csr_read(CSR_MCYCLE)
switchcase_csr_read(CSR_MINSTRET)
switchcase_csr_read(CSR_MHPMCOUNTER3)
switchcase_csr_read_4(CSR_MHPMCOUNTER4)
switchcase_csr_read_8(CSR_MHPMCOUNTER8)
switchcase_csr_read_16(CSR_MHPMCOUNTER16)
switchcase_csr_read(CSR_MCOUNTINHIBIT)
switchcase_csr_read(CSR_MCYCLECFG)
switchcase_csr_read(CSR_MINSTRETCFG)
switchcase_csr_read(CSR_MHPMEVENT3)
switchcase_csr_read_4(CSR_MHPMEVENT4)
switchcase_csr_read_8(CSR_MHPMEVENT8)
switchcase_csr_read_16(CSR_MHPMEVENT16)
#if __riscv_xlen == 32
switchcase_csr_read(CSR_MCYCLEH)
switchcase_csr_read(CSR_MINSTRETH)
switchcase_csr_read(CSR_MHPMCOUNTER3H)
switchcase_csr_read_4(CSR_MHPMCOUNTER4H)
switchcase_csr_read_8(CSR_MHPMCOUNTER8H)
switchcase_csr_read_16(CSR_MHPMCOUNTER16H)
/**
* The CSR range M[CYCLE, INSTRET]CFGH are available only if smcntrpmf
* extension is present. The caller must ensure that.
*/
switchcase_csr_read(CSR_MCYCLECFGH)
switchcase_csr_read(CSR_MINSTRETCFGH)
/**
* The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
* extension is present. The caller must ensure that.
*/
switchcase_csr_read(CSR_MHPMEVENT3H)
switchcase_csr_read_4(CSR_MHPMEVENT4H)
switchcase_csr_read_8(CSR_MHPMEVENT8H)
switchcase_csr_read_16(CSR_MHPMEVENT16H)
#endif
switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE)
switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE)
switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
return 0;
}
#undef switchcase_csr_read_256
#undef switchcase_csr_read_128
#undef switchcase_csr_read_64
#undef switchcase_csr_read_32
#undef switchcase_csr_read_16
#undef switchcase_csr_read_8
#undef switchcase_csr_read_4
#undef switchcase_csr_read_2
#undef switchcase_csr_read
}
void csr_write_num(int csr_num, unsigned long val)
{
#define switchcase_csr_write(__csr_num, __val) \
case __csr_num: \
csr_write(__csr_num, __val); \
break;
#define switchcase_csr_write_2(__csr_num, __val) \
switchcase_csr_write(__csr_num + 0, __val) \
switchcase_csr_write(__csr_num + 1, __val)
#define switchcase_csr_write_4(__csr_num, __val) \
switchcase_csr_write_2(__csr_num + 0, __val) \
switchcase_csr_write_2(__csr_num + 2, __val)
#define switchcase_csr_write_8(__csr_num, __val) \
switchcase_csr_write_4(__csr_num + 0, __val) \
switchcase_csr_write_4(__csr_num + 4, __val)
#define switchcase_csr_write_16(__csr_num, __val) \
switchcase_csr_write_8(__csr_num + 0, __val) \
switchcase_csr_write_8(__csr_num + 8, __val)
#define switchcase_csr_write_32(__csr_num, __val) \
switchcase_csr_write_16(__csr_num + 0, __val) \
switchcase_csr_write_16(__csr_num + 16, __val)
#define switchcase_csr_write_64(__csr_num, __val) \
switchcase_csr_write_32(__csr_num + 0, __val) \
switchcase_csr_write_32(__csr_num + 32, __val)
#define switchcase_csr_write_128(__csr_num, __val) \
switchcase_csr_write_64(__csr_num + 0, __val) \
switchcase_csr_write_64(__csr_num + 64, __val)
#define switchcase_csr_write_256(__csr_num, __val) \
switchcase_csr_write_128(__csr_num + 0, __val) \
switchcase_csr_write_128(__csr_num + 128, __val)
switch (csr_num) {
switchcase_csr_write_16(CSR_PMPCFG0, val)
switchcase_csr_write_64(CSR_PMPADDR0, val)
switchcase_csr_write(CSR_MCYCLE, val)
switchcase_csr_write(CSR_MINSTRET, val)
switchcase_csr_write(CSR_MHPMCOUNTER3, val)
switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
#if __riscv_xlen == 32
switchcase_csr_write(CSR_MCYCLEH, val)
switchcase_csr_write(CSR_MINSTRETH, val)
switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
switchcase_csr_write(CSR_MCYCLECFGH, val)
switchcase_csr_write(CSR_MINSTRETCFGH, val)
switchcase_csr_write(CSR_MHPMEVENT3H, val)
switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
#endif
switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
switchcase_csr_write(CSR_MCYCLECFG, val)
switchcase_csr_write(CSR_MINSTRETCFG, val)
switchcase_csr_write(CSR_MHPMEVENT3, val)
switchcase_csr_write_4(CSR_MHPMEVENT4, val)
switchcase_csr_write_8(CSR_MHPMEVENT8, val)
switchcase_csr_write_16(CSR_MHPMEVENT16, val)
switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val)
switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val)
default:
sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
break;
}
#undef switchcase_csr_write_256
#undef switchcase_csr_write_128
#undef switchcase_csr_write_64
#undef switchcase_csr_write_32
#undef switchcase_csr_write_16
#undef switchcase_csr_write_8
#undef switchcase_csr_write_4
#undef switchcase_csr_write_2
#undef switchcase_csr_write
}
static int hart_pmp_read(pmp_t *pmp, unsigned int n)
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask;
/* check parameters */
if (n >= PMP_COUNT)
return SBI_EINVAL;
/* calculate PMP register and offset */
#if __riscv_xlen == 32
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_shift = (n & 7) << 3;
#else
# error "Unexpected __riscv_xlen"
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
cfgmask = (0xffUL << pmpcfg_shift);
pmp->cfg = (csr_read_num(pmpcfg_csr) & cfgmask) >> pmpcfg_shift;
pmp->addr = csr_read_num(pmpaddr_csr);
return SBI_OK;
}
static int hart_pmp_write(pmp_t *pmp, unsigned int n)
{
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
unsigned long cfgmask, pmpcfg;
/* check parameters */
if (n >= PMP_COUNT)
return SBI_EINVAL;
/* calculate PMP register and offset */
#if __riscv_xlen == 32
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
pmpcfg_shift = (n & 3) << 3;
#elif __riscv_xlen == 64
pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
pmpcfg_shift = (n & 7) << 3;
#else
# error "Unexpected __riscv_xlen"
#endif
pmpaddr_csr = CSR_PMPADDR0 + n;
/* write csrs */
csr_write_num(pmpaddr_csr, pmp->addr);
cfgmask = ~(0xffUL << pmpcfg_shift);
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
pmpcfg |= (((unsigned long)pmp->cfg << pmpcfg_shift) & ~cfgmask);
csr_write_num(pmpcfg_csr, pmpcfg);
return SBI_OK;
}
int sbi_hart_pmp_disable(unsigned int n)
{
pmp_t pmp;
int rc;
rc = hart_pmp_read(&pmp, n);
if (rc)
return rc;
pmp.cfg = 0;
return hart_pmp_write(&pmp, n);
}
bool sbi_hart_is_pmp_enabled(unsigned int n)
{
pmp_t pmp;
if (hart_pmp_read(&pmp, n) != SBI_OK)
return false;
return sbi_pmp_is_enabled(&pmp);
}
int sbi_hart_pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
unsigned long log2len)
{
pmp_t pmp;
int rc;
rc = sbi_pmp_encode(&pmp, prot, addr, log2len);
if (rc)
return rc;
return hart_pmp_write(&pmp, n);
}
int sbi_hart_pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
unsigned long *log2len)
{
pmp_t pmp;
int rc;
rc = hart_pmp_read(&pmp, n);
if (rc)
return rc;
return sbi_pmp_decode(&pmp, prot_out, addr_out, log2len);
}
Reference in New Issue View Git Blame Copy Permalink