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https://github.com/riscv-software-src/opensbi.git
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Pawandeep OzaandAnup Patel
5ee0559445
Add inline register accessors (aplic_sourcecfg_write/read, aplic_target_write, aplic_irq_setie/clrie/clrip, aplic_idc_base/ read/write) to consolidate all MMIO access behind typed helpers and eliminate open-coded address arithmetic throughout the driver. Add field-packing macros APLIC_TARGET_HART_IDX, APLIC_TARGET_IPRIO, and APLIC_TARGET_GUEST_IDX for constructing APLIC_TARGET register values. Add aplic_is_direct_mode() mode helper, aplic_hwirq_flags_to_sourcecfg() to map generic hwirq flags to APLIC source modes, aplic_hwirq_is_delegated() to detect S-mode delegated sources, aplic_find_idc_index() to map a hart index to its IDC slot, and aplic_first_target_hart() to select the first available IDC hart for initial interrupt targeting. Implement the full sbi_irqchip callback set for direct (IDC) mode: - warm_init: enables IDC interrupt delivery and threshold per hart - process_hwirqs: reads TOPI and dispatches via sbi_irqchip_process_hwirq, skipping delegated sources - hwirq_setup: programs sourcecfg from hwirq_flags and sets the TARGET register to the first available IDC hart - hwirq_cleanup: clears IE, IP, sourcecfg, and TARGET on teardown - hwirq_eoi: reads CLAIMI to acknowledge the interrupt on the IDC - hwirq_set_affinity: reprograms TARGET to the specified hart index - hwirq_mask/unmask: clears/sets IE via CLRIENUM/SETIENUM Register the irqchip device and populate target_harts from idc_map only when targets_mmode is set in aplic_cold_irqchip_init(). Co-developed-by: Raymond Mao <raymond.mao@riscstar.com> Signed-off-by Raymond Mao <raymond.mao@riscstar.com> Signed-off-by: Oza Pawandeep <pawandeep.oza@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260721214833.687361-2-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>