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https://github.com/riscv-software-src/opensbi.git
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1f84ec2ac2
Add initial platform support for the SpacemiT K1 SoC, including early/final init hooks, cold boot handling, and CCI-550 snoop/DVM enablement. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/15169E392597D319+aOcKujCl8mz4XK4L@kernel.org/ [1] Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-1-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
99 lines
3.6 KiB
C
99 lines
3.6 KiB
C
#ifndef __RISCV_SPACEMIT_K1_H__
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#define __RISCV_SPACEMIT_K1_H__
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#define CSR_MSETUP 0x7c0
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#define CSR_MHCR 0x7c1
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#define CSR_MRAOP 0x7c2
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#define CSR_MHINT 0x7c5
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#define CSR_ML2SETUP 0x7f0
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/* decache enable */
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#define MSETUP_DE BIT(0)
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/* icache enable */
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#define MSETUP_IE BIT(1)
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/* branch prediction enable */
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#define MSETUP_BPE BIT(4)
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/* prefetch functionality enable */
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#define MSETUP_PFE BIT(5)
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/* misaligned memory access enable */
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#define MSETUP_MME BIT(6)
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/* ECC enable */
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#define MSETUP_ECCE BIT(16)
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/* icache invalidation */
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#define MRAOP_ICACHE_INVALID GENMASK(1, 0)
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#define PMU_AP_BASE 0xd4282800
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#define PMU_AP_CORE0_WAKEUP_OFFSET (PMU_AP_BASE + 0x12c)
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#define PMU_AP_CORE4_WAKEUP_OFFSET (PMU_AP_BASE + 0x324)
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#define PMU_AP_CLUSTER0_WAKEUP_OFFSET(index) (PMU_AP_CORE0_WAKEUP_OFFSET + index * 4)
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#define PMU_AP_CLUSTER1_WAKEUP_OFFSET(index) (PMU_AP_CORE4_WAKEUP_OFFSET + index * 4)
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#define PMU_AP_CORE0_IDLE_CFG_OFFSET (PMU_AP_BASE + 0x124)
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#define PMU_AP_CORE4_IDLE_CFG_OFFSET (PMU_AP_BASE + 0x304)
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#define PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(index) (PMU_AP_CORE0_IDLE_CFG_OFFSET + index * 4)
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#define PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(index) (PMU_AP_CORE4_IDLE_CFG_OFFSET + index * 4)
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#define PMU_AP_CORE0_WAKEUP PMU_AP_CLUSTER0_WAKEUP_OFFSET(0)
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#define PMU_AP_CORE1_WAKEUP PMU_AP_CLUSTER0_WAKEUP_OFFSET(1)
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#define PMU_AP_CORE2_WAKEUP PMU_AP_CLUSTER0_WAKEUP_OFFSET(2)
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#define PMU_AP_CORE3_WAKEUP PMU_AP_CLUSTER0_WAKEUP_OFFSET(3)
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#define PMU_AP_CORE4_WAKEUP PMU_AP_CLUSTER1_WAKEUP_OFFSET(0)
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#define PMU_AP_CORE5_WAKEUP PMU_AP_CLUSTER1_WAKEUP_OFFSET(1)
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#define PMU_AP_CORE6_WAKEUP PMU_AP_CLUSTER1_WAKEUP_OFFSET(2)
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#define PMU_AP_CORE7_WAKEUP PMU_AP_CLUSTER1_WAKEUP_OFFSET(3)
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#define PMU_AP_CORE0_IDLE_CFG PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(0)
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#define PMU_AP_CORE1_IDLE_CFG PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(1)
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#define PMU_AP_CORE2_IDLE_CFG PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(2)
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#define PMU_AP_CORE3_IDLE_CFG PMU_AP_CLUSTER0_IDLE_CFG_OFFSET(3)
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#define PMU_AP_CORE4_IDLE_CFG PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(0)
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#define PMU_AP_CORE5_IDLE_CFG PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(1)
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#define PMU_AP_CORE6_IDLE_CFG PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(2)
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#define PMU_AP_CORE7_IDLE_CFG PMU_AP_CLUSTER1_IDLE_CFG_OFFSET(3)
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/* power down */
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#define PMU_AP_IDLE_PWRDWN BIT(0)
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/* sram power down */
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#define PMU_AP_IDLE_SRAM_PWRDWN BIT(1)
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/* enable wake up the memory controller */
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#define PMU_AP_IDLE_WAKE_MCE BIT(3)
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/* disable memory controller software req */
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#define PMU_AP_IDLE_MC_SW_REQ BIT(4)
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#define PMU_AP_IDLE_PWRDOWN_MASK (PMU_AP_IDLE_PWRDWN | PMU_AP_IDLE_SRAM_PWRDWN | \
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PMU_AP_IDLE_WAKE_MCE | PMU_AP_IDLE_MC_SW_REQ)
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/* cci */
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#define C0_RVBADDR_LO_ADDR 0xd4282db0
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#define C0_RVBADDR_HI_ADDR 0xd4282db4
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#define C1_RVBADDR_LO_ADDR 0xd4282eb0
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#define C1_RVBADDR_HI_ADDR 0xd4282c04
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#define CCI_550_PLATFORM_CCI_ADDR 0xd8500000
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/* relative to cci base */
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#define CCI_550_STATUS 0x000c
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/* status register bits */
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#define CCI_550_STATUS_CHANGE_PENDING BIT(0)
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/* slave interface registers */
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#define CCI_550_SLAVE_IFACE0_OFFSET 0x1000
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#define CCI_550_SLAVE_IFACE_OFFSET(idx) (CCI_550_SLAVE_IFACE0_OFFSET + ((0x1000) * (idx)))
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/* relative to slave interface base */
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#define CCI_550_SNOOP_CTRL 0x0000
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/* snoop control register bits */
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#define CCI_550_SNOOP_CTRL_ENABLE_SNOOPS BIT(0)
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#define CCI_550_SNOOP_CTRL_ENABLE_DVMS BIT(1)
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/* clusters and CPU mapping */
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#define PLATFORM_MAX_CPUS 8
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define CPU_TO_CLUSTER(cpu) ((cpu) / PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLAT_CCI_CLUSTER0_IFACE_IX 0
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#define PLAT_CCI_CLUSTER1_IFACE_IX 1
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#endif
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