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https://github.com/riscv-software-src/opensbi.git
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52ed1d1709
Instead of having separate timer_init() hooks for cold and warm boot, this patch updates struct sbi_platform to have just one timer_init() hook. The type of boot (cold or warm) is now a boolean flag parameter for the updated timer_init() hook. Signed-off-by: Anup Patel <anup.patel@wdc.com>
173 lines
3.8 KiB
C
173 lines
3.8 KiB
C
/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/riscv_io.h>
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#include <plat/irqchip/plic.h>
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#include <plat/serial/sifive-uart.h>
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#include <plat/sys/clint.h>
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#define SIFIVE_U_HART_COUNT 5
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#define SIFIVE_U_HART_STACK_SIZE 8192
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#define SIFIVE_U_SYS_CLK 1000000000
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#define SIFIVE_U_CLINT_ADDR 0x2000000
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#define SIFIVE_U_PLIC_ADDR 0xc000000
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#define SIFIVE_U_PLIC_NUM_SOURCES 0x35
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_UART0_ADDR 0x10010000
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#define SIFIVE_U_UART1_ADDR 0x10011000
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#define SIFIVE_UART_BAUDRATE 115200
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#define SIFIVE_U_HARITD_ENABLED 1
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/* PRCI clock related macros */
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//TODO: Do we need a separate driver for this ?
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#define SIFIVE_PRCI_BASE_ADDR 0x10000000
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#define SIFIVE_PRCI_CLKMUXSTATUSREG 0x002C
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#define SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
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static int sifive_u_final_init(u32 hartid, bool cold_boot)
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{
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u32 i;
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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plic_fdt_fixup(fdt, "riscv,plic0", 0);
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for (i = 1; i < SIFIVE_U_HART_COUNT; i++)
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plic_fdt_fixup(fdt, "riscv,plic0", 2 * i - 1);
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return 0;
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}
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static u32 sifive_u_pmp_region_count(u32 target_hart)
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{
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return 1;
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}
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static int sifive_u_pmp_region_info(u32 target_hart, u32 index,
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ulong *prot, ulong *addr, ulong *log2size)
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{
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int ret = 0;
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switch (index) {
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case 0:
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*prot = PMP_R | PMP_W | PMP_X;
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*addr = 0;
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*log2size = __riscv_xlen;
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break;
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default:
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ret = -1;
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break;
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};
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return ret;
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}
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static int sifive_u_console_init(void)
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{
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unsigned long peri_in_freq;
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if (readl((volatile void *)SIFIVE_PRCI_BASE_ADDR +
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SIFIVE_PRCI_CLKMUXSTATUSREG) &
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SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL){
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peri_in_freq = SIFIVE_U_SYS_CLK;
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} else {
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peri_in_freq = SIFIVE_U_SYS_CLK / 2;
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}
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return sifive_uart_init(SIFIVE_U_UART0_ADDR,
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peri_in_freq, SIFIVE_UART_BAUDRATE);
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}
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static int sifive_u_irqchip_init(u32 hartid, bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = plic_cold_irqchip_init(SIFIVE_U_PLIC_ADDR,
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SIFIVE_U_PLIC_NUM_SOURCES,
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SIFIVE_U_HART_COUNT);
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if (rc)
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return rc;
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}
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return plic_warm_irqchip_init(hartid,
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(hartid) ? (2 * hartid - 1) : 0,
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(hartid) ? (2 * hartid) : -1);
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}
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static int sifive_u_ipi_init(u32 hartid, bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR,
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SIFIVE_U_HART_COUNT);
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if (rc)
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return rc;
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}
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return clint_warm_ipi_init(hartid);
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}
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static int sifive_u_timer_init(u32 hartid, bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = clint_cold_timer_init(SIFIVE_U_CLINT_ADDR,
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SIFIVE_U_HART_COUNT);
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if (rc)
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return rc;
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}
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return clint_warm_timer_init(hartid);
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}
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static int sifive_u_system_down(u32 type)
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{
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/* For now nothing to do. */
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return 0;
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}
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struct sbi_platform platform = {
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.name = "SiFive HiFive U540",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = SIFIVE_U_HART_COUNT,
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.hart_stack_size = SIFIVE_U_HART_STACK_SIZE,
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.disabled_hart_mask = ~(1 << SIFIVE_U_HARITD_ENABLED),
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.pmp_region_count = sifive_u_pmp_region_count,
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.pmp_region_info = sifive_u_pmp_region_info,
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.final_init = sifive_u_final_init,
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.console_putc = sifive_uart_putc,
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.console_getc = sifive_uart_getc,
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.console_init = sifive_u_console_init,
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.irqchip_init = sifive_u_irqchip_init,
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.ipi_inject = clint_ipi_inject,
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.ipi_sync = clint_ipi_sync,
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.ipi_clear = clint_ipi_clear,
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.ipi_init = sifive_u_ipi_init,
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.timer_value = clint_timer_value,
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.timer_event_stop = clint_timer_event_stop,
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.timer_event_start = clint_timer_event_start,
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.timer_init = sifive_u_timer_init,
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.system_reboot = sifive_u_system_down,
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.system_shutdown = sifive_u_system_down
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};
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