Xiang W f465413402 lib: sbi: Allow platforms to override local TLB operations ...

Some T-Head based processors, for example the Sophgo SG2044, have a
JTLB errata that requires special handling of certain TLB maintenance
instructions (sfence.vma).

Introduce a sbi_tlb_local_operations structure so platforms can provide
custom local TLB flush implementations. Use it to implement the JTLB
workaround on affected SoCs (currently Sophgo SG2044).

Signed-off-by: Xiang W <wangxiang@iscas.ac.cn>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260617112925.1144190-2-wangxiang@iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>

2026-08-20 20:30:48 +05:30

..

sbi

lib: sbi: Allow platforms to override local TLB operations

2026-08-20 20:30:48 +05:30

sbi_utils

lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data

2026-07-22 13:08:15 +05:30