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https://github.com/riscv-software-src/opensbi.git
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2b93ce0954
To make the framework suit all Andes CPUs, change all occurrences of andes45 to andes. In addition, we fix some coding style problems and remove an unused macro in andes.h. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2024 Andes Technology Corporation
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*/
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#ifndef _RISCV_ANDES_H
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#define _RISCV_ANDES_H
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/* Memory and Miscellaneous Registers */
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MCCTLCOMMAND 0x7cc
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/* Configuration Control & Status Registers */
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#define CSR_MICM_CFG 0xfc0
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#define CSR_MDCM_CFG 0xfc1
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#define CSR_MMSC_CFG 0xfc2
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/* Machine Trap Related Registers */
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#define CSR_MSLIDELEG 0x7d5
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/* Counter Related Registers */
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#define CSR_MCOUNTERWEN 0x7ce
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#define CSR_MCOUNTERINTEN 0x7cf
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#define CSR_MCOUNTERMASK_M 0x7d1
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#define CSR_MCOUNTERMASK_S 0x7d2
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#define CSR_MCOUNTERMASK_U 0x7d3
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#define CSR_MCOUNTEROVF 0x7d4
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/* PMA Related Registers */
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#define CSR_PMACFG0 0xbc0
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#define CSR_PMAADDR0 0xbd0
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#define MICM_CFG_ISZ_OFFSET 6
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#define MICM_CFG_ISZ_MASK (7 << MICM_CFG_ISZ_OFFSET)
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#define MDCM_CFG_DSZ_OFFSET 6
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#define MDCM_CFG_DSZ_MASK (7 << MDCM_CFG_DSZ_OFFSET)
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#define MMSC_CFG_CCTLCSR_OFFSET 16
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#define MMSC_CFG_CCTLCSR_MASK (1 << MMSC_CFG_CCTLCSR_OFFSET)
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#define MMSC_CFG_PPMA_OFFSET 30
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#define MMSC_CFG_PPMA_MASK (1 << MMSC_CFG_PPMA_OFFSET)
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#define MMSC_IOCP_OFFSET 47
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#define MMSC_IOCP_MASK (1ULL << MMSC_IOCP_OFFSET)
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_CCTL_SUEN_MASK (1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
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/* Performance monitor */
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#define MMSC_CFG_PMNDS_MASK (1 << 15)
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#define MIP_PMOVI (1 << 18)
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#ifndef __ASSEMBLER__
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#define is_andes(series) \
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({ \
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char value = csr_read(CSR_MARCHID) & 0xff; \
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(series) == (value >> 4) * 10 + (value & 0x0f); \
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})
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#define has_andes_pmu() \
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({ \
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(((csr_read(CSR_MMSC_CFG) & \
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MMSC_CFG_PMNDS_MASK) \
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&& misa_extension('S')) ? true : false); \
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})
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#endif /* __ASSEMBLER__ */
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#endif /* _RISCV_ANDES_H */
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