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https://github.com/riscv-software-src/opensbi.git
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2b93ce0954
To make the framework suit all Andes CPUs, change all occurrences of andes45 to andes. In addition, we fix some coding style problems and remove an unused macro in andes.h. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
// SPDX-License-Identifier: BSD-2-Clause
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/*
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* andes_pmu.c - Andes PMU device callbacks and platform overrides
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*
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* Copyright (C) 2023 Andes Technology Corporation
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*/
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#include <andes/andes.h>
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#include <andes/andes_pmu.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_pmu.h>
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#include <libfdt.h>
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static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
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{
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unsigned long mip_val;
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if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
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return;
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mip_val = csr_read(CSR_MIP);
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if (!(mip_val & MIP_PMOVI))
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csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
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csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
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{
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csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
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{
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if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
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csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
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else
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csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
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if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
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csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
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else
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csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
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}
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static struct sbi_pmu_device andes_pmu = {
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.name = "andes_pmu",
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.hw_counter_enable_irq = andes_hw_counter_enable_irq,
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.hw_counter_disable_irq = andes_hw_counter_disable_irq,
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/*
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* We set delegation of supervisor local interrupts via
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* 18th bit on mslideleg instead of mideleg, so leave
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* hw_counter_irq_bit() callback unimplemented.
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*/
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.hw_counter_irq_bit = NULL,
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.hw_counter_filter_mode = andes_hw_counter_filter_mode
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};
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int andes_pmu_extensions_init(const struct fdt_match *match,
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struct sbi_hart_features *hfeatures)
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{
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struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
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if (!has_andes_pmu())
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return 0;
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/*
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* Don't expect both Andes PMU and standard Sscofpmf/Smcntrpmf,
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* are supported as they serve the same purpose.
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*/
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF) ||
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sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
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return SBI_EINVAL;
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sbi_hart_update_extension(scratch, SBI_HART_EXT_XANDESPMU, true);
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/* Inhibit all HPM counters in M-mode */
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csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
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/* Delegate counter overflow interrupt to S-mode */
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csr_write(CSR_MSLIDELEG, MIP_PMOVI);
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return 0;
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}
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int andes_pmu_init(const struct fdt_match *match)
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{
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struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
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sbi_pmu_set_device(&andes_pmu);
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return 0;
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}
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