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https://github.com/riscv-software-src/opensbi.git
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2b93ce0954
To make the framework suit all Andes CPUs, change all occurrences of andes45 to andes. In addition, we fix some coding style problems and remove an unused macro in andes.h. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
124 lines
2.7 KiB
C
124 lines
2.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <platform_override.h>
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#include <andes/andes_pmu.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/sys/atcsmu.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_init.h>
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#include <andes/andes.h>
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static struct smu_data smu = { 0 };
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extern void __ae350_enable_coherency_warmboot(void);
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extern void __ae350_disable_coherency(void);
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static int ae350_hart_start(u32 hartid, ulong saddr)
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{
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/*
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* Don't send wakeup command when:
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* 1) boot-time
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* 2) the target hart is non-sleepable 25-series hart0
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*/
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if (!sbi_init_count(hartid) || (is_andes(25) && hartid == 0))
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return sbi_ipi_raw_send(sbi_hartid_to_hartindex(hartid));
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/* Write wakeup command to the sleep hart */
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smu_set_command(&smu, WAKEUP_CMD, hartid);
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return 0;
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}
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static int ae350_hart_stop(void)
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{
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int rc;
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u32 hartid = current_hartid();
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/**
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* For Andes AX25MP, the hart0 shares power domain with
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* L2-cache, instead of turning it off, it should fall
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* through and jump to warmboot_addr.
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*/
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if (is_andes(25) && hartid == 0)
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return SBI_ENOTSUPP;
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if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
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return SBI_ENOTSUPP;
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/**
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* disable all events, the current hart will be
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* woken up from reset vector when other hart
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* writes its PCS (power control slot) control
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* register
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*/
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smu_set_wakeup_events(&smu, 0x0, hartid);
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smu_set_command(&smu, DEEP_SLEEP_CMD, hartid);
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rc = smu_set_reset_vector(&smu,
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(ulong)__ae350_enable_coherency_warmboot,
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hartid);
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if (rc)
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goto fail;
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__ae350_disable_coherency();
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wfi();
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fail:
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/* It should never reach here */
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sbi_hart_hang();
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return 0;
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}
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static const struct sbi_hsm_device andes_smu = {
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.name = "andes_smu",
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.hart_start = ae350_hart_start,
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.hart_stop = ae350_hart_stop,
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};
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static void ae350_hsm_device_init(void)
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{
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int rc;
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void *fdt;
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fdt = fdt_get_address();
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rc = fdt_parse_compat_addr(fdt, (uint64_t *)&smu.addr,
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"andestech,atcsmu");
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if (!rc) {
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sbi_hsm_set_device(&andes_smu);
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}
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}
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static int ae350_final_init(bool cold_boot, const struct fdt_match *match)
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{
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if (cold_boot)
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ae350_hsm_device_init();
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return 0;
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}
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static const struct fdt_match andes_ae350_match[] = {
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{ .compatible = "andestech,ae350" },
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{ },
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};
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const struct platform_override andes_ae350 = {
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.match_table = andes_ae350_match,
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.final_init = ae350_final_init,
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.extensions_init = andes_pmu_extensions_init,
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.pmu_init = andes_pmu_init,
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};
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