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https://github.com/riscv-software-src/opensbi.git
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434add551c
For driver subsystems that are not tightly integrated into the OpenSBI init sequence, it is not important that the drivers are initialized in any particular order. By putting all of these drivers in one array, they can all be initialized with a single pass through the devicetree. This saves about 10 ms of boot time on HiFive Unmatched. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/fdt/fdt_driver.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/sys/atcsmu.h>
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#define ATCWDT200_WP_NUM 0x5aa5
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#define WREN_REG 0x18
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#define CTRL_REG 0x10
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#define RST_TIME_OFF 8
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#define RST_TIME_MSK (0x3 << RST_TIME_OFF)
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#define RST_CLK_128 (0 << RST_TIME_OFF)
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#define RST_CLK_256 (1 << RST_TIME_OFF)
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#define RST_CLK_512 (2 << RST_TIME_OFF)
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#define RST_CLK_1024 (3 << RST_TIME_OFF)
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#define INT_TIME_OFF 4
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#define INT_TIME_MSK (0xf << INT_TIME_OFF)
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#define INT_CLK_64 (0 << INT_TIME_OFF)
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#define INT_CLK_256 (1 << INT_TIME_OFF)
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#define INT_CLK_1024 (2 << INT_TIME_OFF)
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#define INT_CLK_2048 (3 << INT_TIME_OFF)
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#define INT_CLK_4096 (4 << INT_TIME_OFF)
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#define INT_CLK_8192 (5 << INT_TIME_OFF)
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#define INT_CLK_16384 (6 << INT_TIME_OFF)
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#define INT_CLK_32768 (7 << INT_TIME_OFF)
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#define RST_EN (1 << 3)
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#define INT_EN (1 << 2)
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#define CLK_PCLK (1 << 1)
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#define WDT_EN (1 << 0)
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static volatile char *wdt_addr = NULL;
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static struct smu_data smu = { 0 };
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static int ae350_system_reset_check(u32 type, u32 reason)
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{
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switch (type) {
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case SBI_SRST_RESET_TYPE_COLD_REBOOT:
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return 1;
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case SBI_SRST_RESET_TYPE_SHUTDOWN:
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case SBI_SRST_RESET_TYPE_WARM_REBOOT:
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default:
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return 0;
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}
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}
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static void ae350_system_reset(u32 type, u32 reason)
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{
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const struct sbi_platform *plat = sbi_platform_thishart_ptr();
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for (int i = 0; i < sbi_platform_hart_count(plat); i++)
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if (smu_set_reset_vector(&smu, FLASH_BASE, i))
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goto fail;
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/* Program WDT control register */
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writew(ATCWDT200_WP_NUM, wdt_addr + WREN_REG);
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writel(INT_CLK_32768 | INT_EN | RST_CLK_128 | RST_EN | WDT_EN,
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wdt_addr + CTRL_REG);
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fail:
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sbi_hart_hang();
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}
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static struct sbi_system_reset_device atcwdt200_reset = {
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.name = "atcwdt200",
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.system_reset_check = ae350_system_reset_check,
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.system_reset = ae350_system_reset,
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};
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static int atcwdt200_reset_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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uint64_t reg_addr;
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int rc;
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rc = fdt_get_node_addr_size(fdt, nodeoff, 0, ®_addr, NULL);
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if (rc < 0 || !reg_addr)
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return SBI_ENODEV;
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wdt_addr = (volatile char *)(unsigned long)reg_addr;
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/*
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* The reset device requires smu to program the reset
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* vector for each hart.
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*/
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if (fdt_parse_compat_addr(fdt, ®_addr, "andestech,atcsmu"))
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return SBI_ENODEV;
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smu.addr = (unsigned long)reg_addr;
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sbi_system_reset_add_device(&atcwdt200_reset);
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return 0;
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}
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static const struct fdt_match atcwdt200_reset_match[] = {
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{ .compatible = "andestech,atcwdt200" },
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{},
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};
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const struct fdt_driver fdt_reset_atcwdt200 = {
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.match_table = atcwdt200_reset_match,
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.init = atcwdt200_reset_init,
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};
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