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Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
29 lines
566 B
Plaintext
29 lines
566 B
Plaintext
# SPDX-License-Identifier: BSD-2-Clause
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menu "System Suspend Support"
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config FDT_SUSPEND
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bool "FDT based suspend drivers"
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depends on FDT
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default n
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if FDT_SUSPEND
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config FDT_SUSPEND_ANDES_ATCSMU
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bool "FDT Andes ATCSMU suspend driver"
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depends on FDT_HSM_ANDES_ATCSMU && FDT_CACHE_ANDES_LLCACHE
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default n
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config FDT_SUSPEND_RPMI
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bool "FDT RPMI suspend driver"
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depends on FDT_MAILBOX && RPMI_MAILBOX
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default n
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config FDT_SUSPEND_SIFIVE_SMC0
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bool "FDT SIFIVE SMC0 suspend driver"
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depends on FDT_HSM_SIFIVE_TMC0 && IRQCHIP_APLIC
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default n
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endif
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endmenu
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