Nylon Chen 30ea8069f4 lib: sbi_hart: Enable hcontext and scontext ...

According to the description in "riscv-state-enable[0]", to access
h/scontext in S-Mode, we need to enable the 57th bit.

If it is not enabled, an "illegal instruction" error will occur.

Link: https://github.com/riscv/riscv-state-enable/blob/a28bfae443f350d5b4c42874f428367d5b322ffe/content.adoc [0]

Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

2023-02-27 11:22:11 +05:30

..

sbi

lib: sbi_hart: Enable hcontext and scontext

2023-02-27 11:22:11 +05:30

utils

lib: utils: fdt_fixup: Fix compile error

2023-02-27 10:49:09 +05:30