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https://github.com/riscv-software-src/opensbi.git
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787296ae92
Add hart_start() and hart_stop() callbacks for the multi-core ae350
platform, it utilizes the ATCSMU to put the harts into power-gated
deep sleep mode. The programming sequence is stated as below:
1. Set the wakeup events to PCSm_WE
2. Set the sleep command to PCSm_CTL
3. Set the reset vector to HARTm_RESET_VECTOR_{LO|HI}
4. Write back and invalidate D-cache by executing the CCTL command L1D_WBINVAL_ALL
5. Disable I/D-cache by clearing mcache_ctl.{I|D}C_EN
6. Disable D-cache coherency by clearing mcache_ctl_.DC_COHEN
7. Wait for mcache_ctl.DC_COHSTA to be cleared to ensure the previous step is completed
8. Execute WFI
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
71 lines
1.5 KiB
ArmAsm
71 lines
1.5 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023 Andes Technology Corporation
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*
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* Authors:
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* Yu Chien Peter Lin <peterlin@andestech.com>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_asm.h>
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#include <andes/andes45.h>
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.section .text, "ax", %progbits
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.align 3
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.global __ae350_disable_coherency
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__ae350_disable_coherency:
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/* flush d-cache */
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csrw CSR_MCCTLCOMMAND, 0x6
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/* disable i/d-cache */
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csrc CSR_MCACHE_CTL, 0x3
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/* disable d-cache coherency */
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lui t1, 0x80
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csrc CSR_MCACHE_CTL, t1
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/*
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* wait for mcache_ctl.DC_COHSTA to be cleared,
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* the bit is hard-wired 0 on platforms w/o CM
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* (Coherence Manager)
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*/
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check_cm_disabled:
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csrr t1, CSR_MCACHE_CTL
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srli t1, t1, 20
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andi t1, t1, 0x1
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bnez t1, check_cm_disabled
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ret
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.section .text, "ax", %progbits
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.align 3
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.global __ae350_enable_coherency
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__ae350_enable_coherency:
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/* enable d-cache coherency */
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lui t1, 0x80
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csrs CSR_MCACHE_CTL, t1
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/*
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* mcache_ctl.DC_COHEN is hard-wired 0 on platforms
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* w/o CM support
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*/
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csrr t1, CSR_MCACHE_CTL
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srli t1, t1, 19
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andi t1, t1, 0x1
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beqz t1, enable_L1_cache
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/* wait for mcache_ctl.DC_COHSTA to be set */
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check_cm_enabled:
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csrr t1, CSR_MCACHE_CTL
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srli t1, t1, 20
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andi t1, t1, 0x1
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beqz t1, check_cm_enabled
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enable_L1_cache:
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/* enable i/d-cache */
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csrs CSR_MCACHE_CTL, 0x3
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ret
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.section .text, "ax", %progbits
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.align 3
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.global __ae350_enable_coherency_warmboot
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__ae350_enable_coherency_warmboot:
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call ra, __ae350_enable_coherency
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j _start_warm
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