Dave Patel 21461156da lib: sbi: Add RISC-V vector context save/restore support ...

Eager context switch: Add support for saving and restoring RISC-V vector
extension state in OpenSBI. This introduces a per-hart vector context
structure and helper routines to perform full context save and restore.

The vector context includes vcsr CSRs along with storage for all 32 vector
registers. The register state is saved and restored using byte-wise vector
load/store instructions (vs8r/vl8r).

The implementation follows an eager context switching model where the entire
vector state is saved and restored on every context switch. This provides a
simple and deterministic mechanism without requiring lazy trap-based
management.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260518083023.997323-2-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org>

2026-05-18 14:02:28 +05:30

..

sbi

lib: sbi: Add RISC-V vector context save/restore support

2026-05-18 14:02:28 +05:30

utils

lib: sbi_irqchip: Allow marking hardware interrupts as reserved

2026-05-12 09:55:58 +05:30