mirror of
https://github.com/riscv-software-src/opensbi.git
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10baa64c02
Noisy commit, no functional changes. Generated with an current upstream clang-format and: clang-format -i $(find . -name \*.[ch]) Signed-off-by: Olof Johansson <olof@lixom.net>
119 lines
4.0 KiB
C
119 lines
4.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __RISCV_UNPRIV_H__
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#define __RISCV_UNPRIV_H__
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_bits.h>
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#include <sbi/sbi_types.h>
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#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \
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static inline type load_##type(const type *addr) \
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{ \
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register ulong __mstatus asm("a2"); \
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type val; \
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asm("csrrs %0, " STR(CSR_MSTATUS) ", %3\n" #insn " %1, %2\n" \
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"csrw " STR( \
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CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus), "=&r"(val) \
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: "m"(*addr), "r"(MSTATUS_MPRV)); \
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return val; \
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}
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#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \
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static inline void store_##type(type *addr, type val) \
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{ \
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register ulong __mstatus asm("a3"); \
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asm volatile( \
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"csrrs %0, " STR( \
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CSR_MSTATUS) ", %3\n" #insn " %1, %2\n" \
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"csrw " STR(CSR_MSTATUS) ", %0" \
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: "+&r"(__mstatus) \
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: "r"(val), "m"(*addr), "r"(MSTATUS_MPRV)); \
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}
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
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DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
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DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
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DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
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#if __riscv_xlen == 64
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
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DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
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#else
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
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static inline u64 load_u64(const u64 *addr)
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{
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return load_u32((u32 *)addr) + ((u64)load_u32((u32 *)addr + 1) << 32);
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}
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static inline void store_u64(u64 *addr, u64 val)
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{
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store_u32((u32 *)addr, val);
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store_u32((u32 *)addr + 1, val >> 32);
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}
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#endif
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static inline ulong get_insn(ulong mepc, ulong *mstatus)
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{
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register ulong __mepc asm("a2") = mepc;
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register ulong __mstatus asm("a3");
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ulong val;
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#ifndef __riscv_compressed
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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#if __riscv_xlen == 64
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STR(LWU) " %[insn], (%[addr])\n"
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#else
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STR(LW) " %[insn], (%[addr])\n"
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#endif
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"csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(__mepc));
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#else
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ulong rvc_mask = 3, tmp;
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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"and %[tmp], %[addr], 2\n"
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"bnez %[tmp], 1f\n"
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#if __riscv_xlen == 64
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STR(LWU) " %[insn], (%[addr])\n"
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#else
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STR(LW) " %[insn], (%[addr])\n"
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#endif
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"beq %[tmp], %[rvc_mask], 2f\n"
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"sll %[insn], %[insn], %[xlen_minus_16]\n"
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"srl %[insn], %[insn], %[xlen_minus_16]\n"
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"j 2f\n"
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"1:\n"
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"lhu %[insn], (%[addr])\n"
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"and %[tmp], %[insn], %[rvc_mask]\n"
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"bne %[tmp], %[rvc_mask], 2f\n"
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"lhu %[tmp], 2(%[addr])\n"
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"sll %[tmp], %[tmp], 16\n"
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"add %[insn], %[insn], %[tmp]\n"
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"2: csrw " STR(CSR_MSTATUS) ", %[mstatus]"
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: [mstatus] "+&r"(__mstatus), [insn] "=&r"(val), [tmp] "=&r"(tmp)
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: [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(__mepc),
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[rvc_mask] "r"(rvc_mask), [xlen_minus_16] "i"(__riscv_xlen - 16));
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#endif
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if (mstatus)
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*mstatus = __mstatus;
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return val;
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}
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#endif
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