mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 07:21:22 +01:00
079bf6f0f9
This code has nothing to do with the ISA's registers, it's about the format of ELF relocations. As such, __SIZEOF_LONG__, being a language / ABI-level property, is a more appropriate constant to use. This also makes it easier to support CHERI, where general-purpose registers are extended to be capabilities, not just integers, and so the register size is not the same as the machine word size. This also happens to make it more correct for RV64ILP32, where the registers are 64-bit integers but the ABI is 32-bit (both for long and for the ELF format), though properly supporting that ABI is not part of the motivation here, just a consequence of improving the code for CHERI. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250709232932.37622-2-jrtc27@jrtc27.com Signed-off-by: Anup Patel <anup@brainfault.org>
770 lines
18 KiB
ArmAsm
770 lines
18 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_elf.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_trap.h>
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#define BOOT_LOTTERY_ACQUIRED 1
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#define BOOT_STATUS_BOOT_HART_DONE 1
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.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2
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add \__d0, \__s0, zero
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add \__d1, \__s1, zero
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add \__d2, \__s2, zero
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.endm
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.macro MOV_5R __d0, __s0, __d1, __s1, __d2, __s2, __d3, __s3, __d4, __s4
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add \__d0, \__s0, zero
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add \__d1, \__s1, zero
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add \__d2, \__s2, zero
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add \__d3, \__s3, zero
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add \__d4, \__s4, zero
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.endm
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.macro CLEAR_MDT tmp
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#if __riscv_xlen == 32
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li \tmp, MSTATUSH_MDT
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csrc CSR_MSTATUSH, \tmp
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#else
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li \tmp, MSTATUS_MDT
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csrc CSR_MSTATUS, \tmp
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#endif
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.globl _start
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.globl _start_warm
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_start:
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/* Find preferred boot HART id */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_boot_hart
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add a6, a0, zero
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MOV_3R a0, s0, a1, s1, a2, s2
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li a7, -1
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beq a6, a7, _try_lottery
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/* Jump to relocation wait loop if we are not boot hart */
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bne a0, a6, _wait_for_boot_hart
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_try_lottery:
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/* Jump to relocation wait loop if we don't get relocation lottery */
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lla a6, _boot_lottery
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li a7, BOOT_LOTTERY_ACQUIRED
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#ifdef __riscv_atomic
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amoswap.w a6, a7, (a6)
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bnez a6, _wait_for_boot_hart
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#elif __riscv_zalrsc
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_sc_fail:
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lr.w t0, (a6)
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sc.w t1, a7, (a6)
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bnez t1, _sc_fail
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bnez t0, _wait_for_boot_hart
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#else
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#error "need a or zalrsc"
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#endif
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/* relocate the global table content */
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li t0, FW_TEXT_START /* link start */
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lla t1, _fw_start /* load start */
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sub t2, t1, t0 /* load offset */
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lla t0, __rela_dyn_start
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lla t1, __rela_dyn_end
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beq t0, t1, _relocate_done
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2:
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REG_L t5, __SIZEOF_LONG__(t0) /* t5 <-- relocation info:type */
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li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
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bne t5, t3, 3f
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REG_L t3, 0(t0)
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REG_L t5, (__SIZEOF_LONG__ * 2)(t0) /* t5 <-- addend */
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add t5, t5, t2
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add t3, t3, t2
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REG_S t5, 0(t3) /* store runtime address to the GOT entry */
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3:
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addi t0, t0, (__SIZEOF_LONG__ * 3)
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blt t0, t1, 2b
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_relocate_done:
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/* At this point we are running from link address */
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/* Reset all registers except ra, a0, a1, a2, a3 and a4 for boot HART */
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li ra, 0
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call _reset_regs
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/* Zero-out BSS */
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lla s4, _bss_start
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lla s5, _bss_end
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_bss_zero:
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REG_S zero, (s4)
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add s4, s4, __SIZEOF_POINTER__
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blt s4, s5, _bss_zero
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/* Setup temporary trap handler */
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lla s4, _start_hang
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csrw CSR_MTVEC, s4
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/*
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* While at this point, trap handling is rudimentary, if a trap happens,
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* it will end up in _start_hang which is enough to hook up a GDB. Clear
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* MDT to avoid generating a double trap and thus entering a
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* critical-error state.
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*/
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CLEAR_MDT t0
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/* Setup temporary stack */
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lla s4, _fw_end
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li s5, (SBI_SCRATCH_SIZE * 2)
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add sp, s4, s5
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/* Allow main firmware to save info */
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MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
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call fw_save_info
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MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
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#ifdef FW_FDT_PATH
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/* Override previous arg1 */
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lla a1, fw_fdt_bin
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#endif
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/*
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* Initialize platform
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* Note: The a0 to a4 registers passed to the
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* firmware are parameters to this function.
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*/
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MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
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call fw_platform_init
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add t0, a0, zero
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MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
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add a1, t0, zero
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/* Preload HART details
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* s7 -> HART Count
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* s8 -> HART Stack Size
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* s9 -> Heap Size
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* s10 -> Heap Offset
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*/
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lla a4, platform
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#if __riscv_xlen > 32
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lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
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lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
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lwu s9, SBI_PLATFORM_HEAP_SIZE_OFFSET(a4)
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#else
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lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
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lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
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lw s9, SBI_PLATFORM_HEAP_SIZE_OFFSET(a4)
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#endif
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/* Setup scratch space for all the HARTs*/
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lla tp, _fw_end
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mul a5, s7, s8
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add tp, tp, a5
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/* Setup heap base address */
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lla s10, _fw_start
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sub s10, tp, s10
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add tp, tp, s9
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/* Keep a copy of tp */
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add t3, tp, zero
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/* Counter */
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li t2, 1
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/* hartid 0 is mandated by ISA */
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li t1, 0
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_scratch_init:
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/*
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* The following registers hold values that are computed before
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* entering this block, and should remain unchanged.
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*
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* t3 -> the firmware end address
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* s7 -> HART count
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* s8 -> HART stack size
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* s9 -> Heap Size
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* s10 -> Heap Offset
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*/
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add tp, t3, zero
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sub tp, tp, s9
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mul a5, s8, t1
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sub tp, tp, a5
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li a5, SBI_SCRATCH_SIZE
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sub tp, tp, a5
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/* Initialize scratch space */
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/* Store fw_start and fw_size in scratch space */
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lla a4, _fw_start
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sub a5, t3, a4
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REG_S a4, SBI_SCRATCH_FW_START_OFFSET(tp)
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REG_S a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
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/* Store R/W section's offset in scratch space */
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lla a5, _fw_rw_start
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sub a5, a5, a4
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REG_S a5, SBI_SCRATCH_FW_RW_OFFSET(tp)
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/* Store fw_heap_offset and fw_heap_size in scratch space */
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REG_S s10, SBI_SCRATCH_FW_HEAP_OFFSET(tp)
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REG_S s9, SBI_SCRATCH_FW_HEAP_SIZE_OFFSET(tp)
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/* Store next arg1 in scratch space */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_next_arg1
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REG_S a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
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MOV_3R a0, s0, a1, s1, a2, s2
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/* Store next address in scratch space */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_next_addr
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REG_S a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
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MOV_3R a0, s0, a1, s1, a2, s2
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/* Store next mode in scratch space */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_next_mode
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REG_S a0, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
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MOV_3R a0, s0, a1, s1, a2, s2
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/* Store warm_boot address in scratch space */
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lla a4, _start_warm
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REG_S a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
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/* Store platform address in scratch space */
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lla a4, platform
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REG_S a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
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/* Store hartid-to-scratch function address in scratch space */
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lla a4, _hartid_to_scratch
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REG_S a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
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/* Clear trap_context and tmp0 in scratch space */
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REG_S zero, SBI_SCRATCH_TRAP_CONTEXT_OFFSET(tp)
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REG_S zero, SBI_SCRATCH_TMP0_OFFSET(tp)
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/* Store firmware options in scratch space */
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MOV_3R s0, a0, s1, a1, s2, a2
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#ifdef FW_OPTIONS
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li a0, FW_OPTIONS
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#else
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call fw_options
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#endif
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REG_S a0, SBI_SCRATCH_OPTIONS_OFFSET(tp)
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MOV_3R a0, s0, a1, s1, a2, s2
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/* Store hart index in scratch space */
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REG_S t1, SBI_SCRATCH_HARTINDEX_OFFSET(tp)
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/* Move to next scratch space */
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add t1, t1, t2
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blt t1, s7, _scratch_init
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/*
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* Relocate Flatened Device Tree (FDT)
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* source FDT address = previous arg1
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* destination FDT address = next arg1
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*
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* Note: We will preserve a0 and a1 passed by
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* previous booting stage.
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*/
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beqz a1, _fdt_reloc_done
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/* Mask values in a4 */
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li a4, 0xff
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/* t1 = destination FDT start address */
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MOV_3R s0, a0, s1, a1, s2, a2
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call fw_next_arg1
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add t1, a0, zero
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MOV_3R a0, s0, a1, s1, a2, s2
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beqz t1, _fdt_reloc_done
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beq t1, a1, _fdt_reloc_done
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/* t0 = source FDT start address */
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add t0, a1, zero
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/* t2 = source FDT size (convert from big-endian) */
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lbu t2, 7(t0)
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lbu t3, 6(t0)
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lbu t4, 5(t0)
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lbu t5, 4(t0)
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slli t3, t3, 8
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slli t4, t4, 16
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slli t5, t5, 24
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or t2, t2, t3
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or t2, t2, t4
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or t2, t2, t5
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/* t2 = destination FDT end address */
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add t2, t1, t2
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/* FDT copy loop */
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ble t2, t1, _fdt_reloc_done
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_fdt_reloc_again:
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REG_L t3, 0(t0)
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REG_S t3, 0(t1)
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add t0, t0, __SIZEOF_POINTER__
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add t1, t1, __SIZEOF_POINTER__
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blt t1, t2, _fdt_reloc_again
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_fdt_reloc_done:
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/* mark boot hart done */
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li t0, BOOT_STATUS_BOOT_HART_DONE
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lla t1, _boot_status
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fence rw, rw
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REG_S t0, 0(t1)
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j _start_warm
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/* waiting for boot hart to be done (_boot_status == BOOT_STATUS_BOOT_HART_DONE) */
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_wait_for_boot_hart:
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li t0, BOOT_STATUS_BOOT_HART_DONE
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lla t1, _boot_status
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REG_L t1, 0(t1)
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/* Reduce the bus traffic so that boot hart may proceed faster */
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div t2, t2, zero
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div t2, t2, zero
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div t2, t2, zero
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bne t0, t1, _wait_for_boot_hart
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_start_warm:
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/* Reset all registers except ra, a0, a1, a2, a3 and a4 for non-boot HART */
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li ra, 0
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call _reset_regs
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/* Disable all interrupts */
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csrw CSR_MIE, zero
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/* Find HART count and HART stack size */
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lla a4, platform
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#if __riscv_xlen > 32
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lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
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lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
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#else
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lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
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lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
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#endif
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REG_L s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
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/* Find HART id */
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csrr s6, CSR_MHARTID
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/* Find HART index */
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beqz s9, 3f
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li a4, 0
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1:
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#if __riscv_xlen > 32
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lwu a5, (s9)
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#else
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lw a5, (s9)
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#endif
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beq a5, s6, 2f
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add s9, s9, 4
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add a4, a4, 1
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blt a4, s7, 1b
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2: add s6, a4, zero
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3: bge s6, s7, _start_hang
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/* Find the scratch space based on HART index */
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lla tp, _fw_end
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mul a5, s7, s8
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add tp, tp, a5
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mul a5, s8, s6
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sub tp, tp, a5
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li a5, SBI_SCRATCH_SIZE
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sub tp, tp, a5
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/* update the mscratch */
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csrw CSR_MSCRATCH, tp
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/* Setup stack */
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add sp, tp, zero
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/* Setup trap handler */
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lla a4, _trap_handler
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csrr a5, CSR_MISA
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srli a5, a5, ('H' - 'A')
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andi a5, a5, 0x1
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beq a5, zero, _skip_trap_handler_hyp
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lla a4, _trap_handler_hyp
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_skip_trap_handler_hyp:
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csrw CSR_MTVEC, a4
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/* Clear MDT here again for all harts */
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CLEAR_MDT t0
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/* Initialize SBI runtime */
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csrr a0, CSR_MSCRATCH
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call sbi_init
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/* We don't expect to reach here hence just hang */
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j _start_hang
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.data
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.align 3
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_boot_lottery:
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RISCV_PTR 0
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_boot_status:
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RISCV_PTR 0
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.section .entry, "ax", %progbits
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.align 3
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.globl _hartid_to_scratch
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_hartid_to_scratch:
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/*
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* a0 -> HART ID (passed by caller)
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* a1 -> HART Index (passed by caller)
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* t0 -> HART Stack Size
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* t1 -> HART Stack End
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* t2 -> Temporary
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*/
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lla t2, platform
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#if __riscv_xlen > 32
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lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
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lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
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#else
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lw t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
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lw t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
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#endif
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sub t2, t2, a1
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mul t2, t2, t0
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lla t1, _fw_end
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add t1, t1, t2
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li t2, SBI_SCRATCH_SIZE
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sub a0, t1, t2
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ret
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.section .entry, "ax", %progbits
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.align 3
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.globl _start_hang
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_start_hang:
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wfi
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j _start_hang
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.section .entry, "ax", %progbits
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.align 3
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.weak fw_platform_init
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fw_platform_init:
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add a0, a1, zero
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ret
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/* Map implicit memcpy() added by compiler to sbi_memcpy() */
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.section .text
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.align 3
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.globl memcpy
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memcpy:
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tail sbi_memcpy
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/* Map implicit memset() added by compiler to sbi_memset() */
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.section .text
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.align 3
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.globl memset
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memset:
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tail sbi_memset
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/* Map implicit memmove() added by compiler to sbi_memmove() */
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.section .text
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.align 3
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.globl memmove
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memmove:
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tail sbi_memmove
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/* Map implicit memcmp() added by compiler to sbi_memcmp() */
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.section .text
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.align 3
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.globl memcmp
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memcmp:
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tail sbi_memcmp
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.macro TRAP_SAVE_AND_SETUP_SP_T0
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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/* Save T0 in scratch space */
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REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
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/*
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* Set T0 to appropriate exception stack
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*
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* Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
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* Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
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*
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* Came_From_M_Mode = 0 ==> Exception_Stack = TP
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* Came_From_M_Mode = -1 ==> Exception_Stack = SP
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*/
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csrr t0, CSR_MSTATUS
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srl t0, t0, MSTATUS_MPP_SHIFT
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and t0, t0, PRV_M
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slti t0, t0, PRV_M
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add t0, t0, -1
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xor sp, sp, tp
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and t0, t0, sp
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xor sp, sp, tp
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xor t0, tp, t0
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/* Save original SP on exception stack */
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REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_CONTEXT_SIZE)(t0)
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/* Set SP to exception stack and make room for trap context */
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add sp, t0, -(SBI_TRAP_CONTEXT_SIZE)
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/* Restore T0 from scratch space */
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REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
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/* Save T0 on stack */
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REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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.endm
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.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
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/* Save MEPC and MSTATUS CSRs */
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csrr t0, CSR_MEPC
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REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrr t0, CSR_MSTATUS
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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.if \have_mstatush
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csrr t0, CSR_MSTATUSH
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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.else
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REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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.endif
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.endm
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.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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/* Save all general regisers except SP and T0 */
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REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
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REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
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REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
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REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
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REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
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REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
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REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
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REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
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REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
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REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
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REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
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REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
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REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
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REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
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REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
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REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
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REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
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REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
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REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
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REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
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REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
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REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
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REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
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REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
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REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
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REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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.endm
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.macro TRAP_SAVE_INFO have_mstatush have_h_extension
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csrr t0, CSR_MCAUSE
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REG_S t0, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(cause))(sp)
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csrr t0, CSR_MTVAL
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REG_S t0, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(tval))(sp)
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.if \have_h_extension
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csrr t0, CSR_MTVAL2
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REG_S t0, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(tval2))(sp)
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csrr t0, CSR_MTINST
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REG_S t0, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(tinst))(sp)
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.if \have_mstatush
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csrr t0, CSR_MSTATUSH
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srli t0, t0, MSTATUSH_GVA_SHIFT
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.else
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csrr t0, CSR_MSTATUS
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srli t0, t0, MSTATUS_GVA_SHIFT
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.endif
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and t0, t0, 0x1
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.else
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REG_S zero, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(tval2))(sp)
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REG_S zero, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(tinst))(sp)
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li t0, 0
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.endif
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REG_S t0, (SBI_TRAP_REGS_SIZE + SBI_TRAP_INFO_OFFSET(gva))(sp)
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/* We are ready to take another trap, clear MDT */
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CLEAR_MDT t0
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.endm
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.macro TRAP_CALL_C_ROUTINE
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/* Call C routine */
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add a0, sp, zero
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call sbi_trap_handler
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.endm
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.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
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/* Restore all general regisers except A0 and T0 */
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REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
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REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
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REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
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REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
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REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
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REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
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REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
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REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
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REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
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REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
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REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
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REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
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REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
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REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
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REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
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REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
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REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
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REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
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REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
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REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
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REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
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REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
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REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
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REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
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REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
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REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
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REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
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REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
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REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
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.endm
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.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
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/*
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* Restore MSTATUS and MEPC CSRs starting with MSTATUS/H to set MDT
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* flags since we can not take a trap now or MEPC would be cloberred
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*/
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.if \have_mstatush
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
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csrw CSR_MSTATUSH, t0
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.endif
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
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csrw CSR_MSTATUS, t0
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REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
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csrw CSR_MEPC, t0
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.endm
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.macro TRAP_RESTORE_A0_T0
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/* Restore T0 */
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REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
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/* Restore A0 */
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REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler
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_trap_handler:
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TRAP_SAVE_AND_SETUP_SP_T0
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TRAP_SAVE_MEPC_MSTATUS 0
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TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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TRAP_SAVE_INFO 0 0
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TRAP_CALL_C_ROUTINE
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TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
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TRAP_RESTORE_MEPC_MSTATUS 0
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TRAP_RESTORE_A0_T0
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mret
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler_hyp
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_trap_handler_hyp:
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TRAP_SAVE_AND_SETUP_SP_T0
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#if __riscv_xlen == 32
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TRAP_SAVE_MEPC_MSTATUS 1
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#else
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TRAP_SAVE_MEPC_MSTATUS 0
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#endif
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TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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#if __riscv_xlen == 32
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TRAP_SAVE_INFO 1 1
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#else
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TRAP_SAVE_INFO 0 1
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#endif
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TRAP_CALL_C_ROUTINE
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TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
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#if __riscv_xlen == 32
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TRAP_RESTORE_MEPC_MSTATUS 1
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#else
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TRAP_RESTORE_MEPC_MSTATUS 0
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#endif
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TRAP_RESTORE_A0_T0
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mret
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.section .entry, "ax", %progbits
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.align 3
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.globl _reset_regs
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_reset_regs:
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/* flush the instruction cache */
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fence.i
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/* Reset all registers except ra, a0, a1, a2, a3 and a4 */
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li sp, 0
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li gp, 0
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li tp, 0
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li t0, 0
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li t1, 0
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li t2, 0
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li s0, 0
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li s1, 0
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li a5, 0
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li a6, 0
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li a7, 0
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li s2, 0
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li s3, 0
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li s4, 0
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li s5, 0
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li s6, 0
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li s7, 0
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li s8, 0
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li s9, 0
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li s10, 0
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li s11, 0
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li t3, 0
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li t4, 0
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li t5, 0
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li t6, 0
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csrw CSR_MSCRATCH, 0
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ret
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.section .rodata
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.Lstack_corrupt_msg:
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.string "stack smashing detected\n"
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/* This will be called when the stack corruption is detected */
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.section .text
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.align 3
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.globl __stack_chk_fail
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.type __stack_chk_fail, %function
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__stack_chk_fail:
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la a0, .Lstack_corrupt_msg
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call sbi_panic
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/* Initial value of the stack guard variable */
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.section .data
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.align 3
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.globl __stack_chk_guard
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.type __stack_chk_guard, %object
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__stack_chk_guard:
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RISCV_PTR 0x95B5FF5A
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#ifdef FW_FDT_PATH
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.section .rodata
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.align 4
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.globl fw_fdt_bin
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fw_fdt_bin:
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.incbin FW_FDT_PATH
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#ifdef FW_FDT_PADDING
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.fill FW_FDT_PADDING, 1, 0
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#endif
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#endif
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