Atish Patra 007a6b26d9 firmware: Reset all registers and flush icache ...

A warm reset using reset button may put icache and registers
in non-coherent state.

Flush the icache and reset all registers for every hart.

Signed-off-by: Atish Patra <atish.patra@wdc.com>

2019-03-07 08:07:18 +05:30

..

payloads

firmware: Use CSR_<FOO> instead of <foo> for csr*

2019-02-14 09:31:18 +05:30

external_deps.mk

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_base.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_base.S

firmware: Reset all registers and flush icache

2019-03-07 08:07:18 +05:30

fw_jump.elf.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_jump.S

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_payload.elf.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_payload.S

firmware: Ensure the payloads are 4 bit alligned

2019-02-15 09:56:47 +05:30

objects.mk

firwmare: don't expand macros in FW_PAYLOAD_PATH

2019-02-06 10:39:17 +05:30