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https://github.com/riscv-software-src/opensbi.git
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8408845cc9
Extend generic platform to support Andes QiLai SoC. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250814104024.3374698-1-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Andes Technology Corporation
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*
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*/
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#include <andes/andes_pma.h>
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#include <andes/andes_pmu.h>
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#include <andes/andes_sbi.h>
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#include <andes/qilai.h>
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#include <platform_override.h>
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#include <sbi/sbi_domain.h>
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#include <sbi_utils/fdt/fdt_driver.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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static int andes_qilai_final_init(bool cold_boot)
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{
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int rc;
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/*
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* Set the memory attribute for 3 PCIE endpoint regions,
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* and they are all non-idempotent and non-bufferable.
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*/
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rc = andes_sbi_set_pma((unsigned long)PCIE0_BASE, (unsigned long)PCIE0_SIZE,
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ANDES_PMACFG_ETYP_NAPOT |
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ANDES_PMACFG_MTYP_DEV_NOBUF);
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if (rc)
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return rc;
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rc = andes_sbi_set_pma((unsigned long)PCIE1_BASE, (unsigned long)PCIE1_SIZE,
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ANDES_PMACFG_ETYP_NAPOT |
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ANDES_PMACFG_MTYP_DEV_NOBUF);
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if (rc)
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return rc;
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rc = andes_sbi_set_pma((unsigned long)PCIE2_BASE, (unsigned long)PCIE2_SIZE,
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ANDES_PMACFG_ETYP_NAPOT |
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ANDES_PMACFG_MTYP_DEV_NOBUF);
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if (rc)
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return rc;
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return generic_final_init(cold_boot);
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}
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static int andes_qilai_platform_init(const void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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generic_platform_ops.final_init = andes_qilai_final_init;
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generic_platform_ops.extensions_init = andes_pmu_extensions_init;
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generic_platform_ops.pmu_init = andes_pmu_init;
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generic_platform_ops.vendor_ext_provider =
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andes_sbi_vendor_ext_provider;
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return 0;
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}
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static const struct fdt_match andes_qilai_match[] = {
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{ .compatible = "andestech,qilai" },
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{},
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};
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const struct fdt_driver andes_qilai = {
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.match_table = andes_qilai_match,
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.init = andes_qilai_platform_init,
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};
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