adds riscv_vp platform

docs/platform/fpga-openpiton.md

@@ -7,8 +7,8 @@ processor from ETH Zurich. To this end, Ariane has been equipped with a
 different L1 cache subsystem that follows a write-through protocol and that has
 support for cache invalidations and atomics.
 
-To build platform specific library and firmwares, provide the *PLATFORM=generic*
+To build platform specific library and firmwares, provide the
-parameter to the top level `make` command.
+*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -21,7 +21,7 @@ Building Ariane FPGA Platform
 **Linux Kernel Payload**
 
 ```
-make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Booting Ariane FPGA Platform

docs/platform/generic.md

@@ -47,7 +47,6 @@ RISC-V Platforms Using Generic Platform
 * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
 * **Spike** (*[spike.md]*)
 * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
-* **OpenPiton FPGA SoC** (*[fpga-openpiton.md]*)
 
 [andes-ae350.md]: andes-ae350.md
 [qemu_virt.md]: qemu_virt.md
@@ -56,4 +55,3 @@ RISC-V Platforms Using Generic Platform
 [sifive_fu540.md]: sifive_fu540.md
 [spike.md]: spike.md
 [thead-c9xx.md]: thead-c9xx.md
-[fpga-openpiton.md]: fpga-openpiton.md

docs/platform/platform.md

@@ -31,6 +31,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
 * **Spike**: Platform support for the Spike emulator. More
   details on this platform can be found in the file *[spike.md]*.
 
+* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based
+  on ariane core. More details on this platform can be found in the file
+  *[fpga-openpiton.md]*.
+
 * **Shakti C-class SoC Platform**: Platform support for Shakti C-class
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
@@ -52,5 +56,6 @@ comments to facilitate the implementation.
 [andes-ae350.md]: andes-ae350.md
 [thead-c910.md]: thead-c910.md
 [spike.md]: spike.md
+[fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
 [renesas-rzfive.md]: renesas-rzfive.md

lib/sbi/sbi_pmu.c

@@ -780,7 +780,6 @@ static int pmu_ctr_find_hw(struct sbi_pmu_hart_state *phs,
 				continue;
 			/* We found a valid counter that is not started yet */
 			ctr_idx = cbase;
-			break;
 		}
 	}
 

platform/fpga/openpiton/Kconfig

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+config PLATFORM_OPENPITON_FPGA
+	bool
+	select FDT
+	select IPI_MSWI
+	select IRQCHIP_PLIC
+	select SERIAL_UART8250
+	select TIMER_MTIMER
+	default y

platform/fpga/openpiton/objects.mk

@@ -0,0 +1,41 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2020 Western Digital Corporation or its affiliates.
+#
+
+# Compiler flags
+platform-cppflags-y =
+platform-cflags-y =
+platform-asflags-y =
+platform-ldflags-y =
+
+# Objects to build
+platform-objs-y += platform.o
+
+PLATFORM_RISCV_XLEN = 64
+
+# Blobs to build
+FW_JUMP=n
+
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+ # This needs to be 4MB aligned for 32-bit support
+ FW_JUMP_ADDR=0x80400000
+ else
+ # This needs to be 2MB aligned for 64-bit support
+ FW_JUMP_ADDR=0x80200000
+ endif
+FW_JUMP_FDT_ADDR=0x82200000
+
+# Firmware with payload configuration.
+FW_PAYLOAD=y
+
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# This needs to be 4MB aligned for 32-bit support
+  FW_PAYLOAD_OFFSET=0x400000
+else
+# This needs to be 2MB aligned for 64-bit support
+  FW_PAYLOAD_OFFSET=0x200000
+endif
+FW_PAYLOAD_FDT_ADDR=0x82200000
+FW_PAYLOAD_ALIGN=0x1000

platform/fpga/openpiton/platform.c

@@ -3,7 +3,12 @@
  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  */
 
-#include <platform_override.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_platform.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/fdt/fdt_fixup.h>
 #include <sbi_utils/ipi/aclint_mswi.h>
@@ -11,19 +16,19 @@
 #include <sbi_utils/serial/uart8250.h>
 #include <sbi_utils/timer/aclint_mtimer.h>
 
-#define OPENPITON_DEFAULT_UART_ADDR		0xfff0c2c000ULL
+#define OPENPITON_DEFAULT_UART_ADDR		0xfff0c2c000
 #define OPENPITON_DEFAULT_UART_FREQ		60000000
 #define OPENPITON_DEFAULT_UART_BAUDRATE		115200
 #define OPENPITON_DEFAULT_UART_REG_SHIFT	0
 #define OPENPITON_DEFAULT_UART_REG_WIDTH	1
 #define OPENPITON_DEFAULT_UART_REG_OFFSET	0
 #define OPENPITON_DEFAULT_UART_CAPS		0
-#define OPENPITON_DEFAULT_PLIC_ADDR		0xfff1100000ULL
+#define OPENPITON_DEFAULT_PLIC_ADDR		0xfff1100000
 #define OPENPITON_DEFAULT_PLIC_SIZE		(0x200000 + \
 				(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
 #define OPENPITON_DEFAULT_PLIC_NUM_SOURCES	2
 #define OPENPITON_DEFAULT_HART_COUNT		3
-#define OPENPITON_DEFAULT_CLINT_ADDR		0xfff1020000ULL
+#define OPENPITON_DEFAULT_CLINT_ADDR		0xfff1020000
 #define OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ	1000000
 #define OPENPITON_DEFAULT_ACLINT_MSWI_ADDR	\
 		(OPENPITON_DEFAULT_CLINT_ADDR + CLINT_MSWI_OFFSET)
@@ -31,12 +36,12 @@
 		(OPENPITON_DEFAULT_CLINT_ADDR + CLINT_MTIMER_OFFSET)
 
 static struct platform_uart_data uart = {
-	(unsigned long)OPENPITON_DEFAULT_UART_ADDR,
+	OPENPITON_DEFAULT_UART_ADDR,
 	OPENPITON_DEFAULT_UART_FREQ,
 	OPENPITON_DEFAULT_UART_BAUDRATE,
 };
 static struct plic_data plic = {
-	.addr = (unsigned long)OPENPITON_DEFAULT_PLIC_ADDR,
+	.addr = OPENPITON_DEFAULT_PLIC_ADDR,
 	.size = OPENPITON_DEFAULT_PLIC_SIZE,
 	.num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
 	.flags = PLIC_FLAG_ARIANE_BUG,
@@ -48,7 +53,7 @@ static struct plic_data plic = {
 };
 
 static struct aclint_mswi_data mswi = {
-	.addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MSWI_ADDR,
+	.addr = OPENPITON_DEFAULT_ACLINT_MSWI_ADDR,
 	.size = ACLINT_MSWI_SIZE,
 	.first_hartid = 0,
 	.hart_count = OPENPITON_DEFAULT_HART_COUNT,
@@ -56,10 +61,10 @@ static struct aclint_mswi_data mswi = {
 
 static struct aclint_mtimer_data mtimer = {
 	.mtime_freq = OPENPITON_DEFAULT_ACLINT_MTIMER_FREQ,
-	.mtime_addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+	.mtime_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
 		      ACLINT_DEFAULT_MTIME_OFFSET,
 	.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
-	.mtimecmp_addr = (unsigned long)OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
+	.mtimecmp_addr = OPENPITON_DEFAULT_ACLINT_MTIMER_ADDR +
 			 ACLINT_DEFAULT_MTIMECMP_OFFSET,
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
@@ -151,23 +156,25 @@ static int openpiton_timer_init(void)
 	return aclint_mtimer_cold_init(&mtimer, NULL);
 }
 
-static int openhwgroup_openpiton_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
+/*
-{
+ * Platform descriptor.
-	generic_platform_ops.early_init = openpiton_early_init;
+ */
-	generic_platform_ops.timer_init = openpiton_timer_init;
+const struct sbi_platform_operations platform_ops = {
-	generic_platform_ops.ipi_init = openpiton_ipi_init;
+	.early_init = openpiton_early_init,
-	generic_platform_ops.irqchip_init = openpiton_irqchip_init;
+	.final_init = openpiton_final_init,
-	generic_platform_ops.final_init = openpiton_final_init;
+	.irqchip_init = openpiton_irqchip_init,
-
+	.ipi_init = openpiton_ipi_init,
-	return 0;
+	.timer_init = openpiton_timer_init,
-}
-
-static const struct fdt_match openhwgroup_openpiton_match[] = {
-	{ .compatible = "openpiton,cva6platform" },
-	{ },
 };
 
-const struct fdt_driver openhwgroup_openpiton = {
+const struct sbi_platform platform = {
-	.match_table = openhwgroup_openpiton_match,
+	.opensbi_version = OPENSBI_VERSION,
-	.init = openhwgroup_openpiton_platform_init,
+	.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+	.name = "OPENPITON RISC-V",
+	.features = SBI_PLATFORM_DEFAULT_FEATURES,
+	.hart_count = OPENPITON_DEFAULT_HART_COUNT,
+	.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
+	.heap_size =
+		SBI_PLATFORM_DEFAULT_HEAP_SIZE(OPENPITON_DEFAULT_HART_COUNT),
+	.platform_ops_addr = (unsigned long)&platform_ops
 };

platform/generic/Kconfig

@@ -36,10 +36,6 @@ config PLATFORM_ANDES_AE350
 	select ANDES_PMA
 	default n
 
-config PLATFORM_OPENHWGROUP_OPENPITON
-	bool "OpenHWGroup Openpiton support"
-	default n
-
 config PLATFORM_RENESAS_RZFIVE
 	bool "Renesas RZ/Five support"
 	select ANDES_PMA

platform/generic/configs/defconfig

@@ -7,7 +7,6 @@ CONFIG_PLATFORM_SOPHGO_SG2042=y
 CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_PLATFORM_THEAD=y
 CONFIG_PLATFORM_MIPS_P8700=y
-CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y
 CONFIG_FDT_CPPC=y
 CONFIG_FDT_CPPC_RPMI=y
 CONFIG_FDT_GPIO=y

platform/generic/openhwgroup/objects.mk

@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-# Copyright (c) 2020 Western Digital Corporation or its affiliates.
-#
-
-carray-platform_override_modules-$(CONFIG_PLATFORM_OPENHWGROUP_OPENPITON) += openhwgroup_openpiton
-platform-objs-$(CONFIG_PLATFORM_OPENHWGROUP_OPENPITON) += openhwgroup/openpiton.o

platform/riscv_vp/Kconfig

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+#
+# All mandatory drivers or libraries for this platform should
+# be directly selected by the PLATFORM_xyz kconfig symbol.
+#
+# All optional drivers or libraries for this platform should
+# be enabled via configs/defconfig of this platform.
+#
+config PLATFORM_TEMPLATE
+	bool
+	select IPI_MSWI
+	select IRQCHIP_PLIC
+	select SERIAL_UART8250
+	select TIMER_MTIMER
+	default n

platform/riscv_vp/objects.mk

@@ -0,0 +1,99 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+#
+
+# Compiler pre-processor flags
+platform-cppflags-y =
+
+# C Compiler and assembler flags.
+platform-cflags-y =
+platform-asflags-y =
+
+# Linker flags: additional libraries and object files that the platform
+# code needs can be added here
+platform-ldflags-y =
+
+#
+# Command for platform specific "make run"
+# Useful for development and debugging on plaftform simulator (such as QEMU)
+#
+# platform-runcmd = your_platform_run.sh
+
+#
+# Platform RISC-V XLEN, ABI, ISA and Code Model configuration.
+# These are optional parameters but platforms can optionaly provide it.
+# Some of these are guessed based on GCC compiler capabilities
+#
+PLATFORM_RISCV_XLEN = 64
+PLATFORM_RISCV_ABI = lp64d
+PLATFORM_RISCV_ISA = rv64imafdc_zicsr_zifencei
+PLATFORM_RISCV_CODE_MODEL = medany
+
+# Space separated list of object file names to be compiled for the platform
+platform-objs-y += platform.o
+
+#
+# If the platform support requires a builtin device tree file, the name of
+# the device tree compiled file should be specified here. The device tree
+# source file be in the form <dt file name>.dts
+#
+# platform-objs-y += <dt file name>.o
+
+# Optional parameter for path to external FDT
+# FW_FDT_PATH="path to platform flattened device tree file"
+
+#
+# Dynamic firmware configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_DYNAMIC=n
+
+#
+# Jump firmware configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_JUMP=n
+# This needs to be 4MB aligned for 32-bit support
+# This needs to be 2MB aligned for 64-bit support
+# ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# FW_JUMP_OFFSET=0x400000
+# else
+# FW_JUMP_OFFSET=0x200000
+# endif
+# FW_JUMP_FDT_OFFSET=0x2200000
+#
+# You can use fixed address for jump firmware as an alternative option.
+# SBI will prefer "<X>_ADDR" if both "<X>_ADDR" and "<X>_OFFSET" are
+# defined
+# ifeq ($(PLATFORM_RISCV_XLEN), 32)
+# FW_JUMP_ADDR=0x80400000
+# else
+# FW_JUMP_ADDR=0x80200000
+# endif
+# FW_JUMP_FDT_ADDR=0x82200000
+
+#
+# Firmware with payload configuration.
+# Optional parameters are commented out. Uncomment and define these parameters
+# as needed.
+#
+FW_PAYLOAD=y
+# This needs to be 4MB aligned for 32-bit support
+# This needs to be 2MB aligned for 64-bit support
+ifeq ($(PLATFORM_RISCV_XLEN), 32)
+FW_PAYLOAD_OFFSET=0x400000
+else
+FW_PAYLOAD_OFFSET=0x200000
+endif
+# FW_PAYLOAD_ALIGN=0x1000
+# FW_PAYLOAD_PATH="path to next boot stage binary image file"
+# FW_PAYLOAD_FDT_OFFSET=0x2200000
+#
+# You can use fixed address for payload firmware as an alternative option.
+# SBI will prefer "FW_PAYLOAD_FDT_ADDR" if both "FW_PAYLOAD_FDT_OFFSET"
+# and "FW_PAYLOAD_FDT_ADDR" are defined.
+# FW_PAYLOAD_FDT_ADDR=0x82200000

platform/riscv_vp/platform.c

@@ -0,0 +1,178 @@
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_system.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_timer.h>
+
+typedef struct {
+  volatile uint32_t RX_TX_REG;
+  volatile uint32_t INT_CTRL_REG;
+  volatile uint32_t CLK_DIVIDER_REG;
+  volatile uint32_t FRAME_CONFIG_REG;
+  volatile uint32_t STATUS_REG;
+} uart_t;
+
+typedef struct {
+  volatile uint32_t MSIP0;
+  uint8_t fill0[16380];
+  volatile uint32_t MTIMECMP0LO;
+  volatile uint32_t MTIMECMP0HI;
+  uint8_t fill1[32752];
+  volatile uint32_t MTIME_LO;
+  volatile uint32_t MTIME_HI;
+} aclint_t;
+
+#define PERIPH(TYPE, ADDR) ((volatile TYPE *)(ADDR))
+#define uart PERIPH(uart_t, 0x10000000 + 0x01000)
+#define aclint PERIPH(aclint_t, 0x10000000 + 0x30000)
+static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
+  reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
+static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
+
+static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
+static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
+  reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
+static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
+
+static void riscv_vp_putc(char c){
+	while(get_uart_rx_tx_reg_tx_free(uart) == 0)
+	;
+    set_uart_rx_tx_reg_data(uart, c);
+}
+static int riscv_vp_getc(){
+    if (get_uart_rx_tx_reg_rx_avail(uart))
+        return get_uart_rx_tx_reg_data(uart);
+    else
+        return -1;
+}
+const struct sbi_console_device minres_console = {
+    .name = "riscv_vp-uart",
+    .console_putc = riscv_vp_putc,
+    .console_getc = riscv_vp_getc,
+};
+
+void riscv_vp_reset(u32 reset_type, u32 reset_reason){
+    switch (reset_type) {
+      case SBI_SRST_RESET_TYPE_SHUTDOWN:
+          sbi_printf("Shutting down system...\n");
+          break;
+      case SBI_SRST_RESET_TYPE_COLD_REBOOT:
+          sbi_printf("Performing cold reboot...\n");
+          break;
+      case SBI_SRST_RESET_TYPE_WARM_REBOOT:
+          sbi_printf("Performing warm reboot...\n");
+          break;
+      default:
+          sbi_printf("Unknown system reset type: %u\n", reset_type);
+  }
+  while (1)
+    wfi();
+};
+int riscv_vp_reset_check(u32 reset_type, u32 reset_reason){
+    switch (reset_type) {
+      case SBI_SRST_RESET_TYPE_SHUTDOWN:
+          return 1;
+      case SBI_SRST_RESET_TYPE_COLD_REBOOT:
+      case SBI_SRST_RESET_TYPE_WARM_REBOOT:
+      default:
+          return 0;
+  }};
+
+
+static struct sbi_system_reset_device reset_device = {
+    .name = "riscv_vp-reset",
+    .system_reset_check = riscv_vp_reset_check,
+    .system_reset = riscv_vp_reset
+};
+
+static u64 riscv_vp_timer_value(void){
+    uint32_t hi, lo;
+    do {
+        hi = get_aclint_mtime_hi(aclint);
+        lo = get_aclint_mtime_lo(aclint);
+    } while (hi != get_aclint_mtime_hi(aclint));
+    return ((u64)hi << 32) | lo;
+}
+static void riscv_vp_timer_event_start(u64 next_event){
+    // sbi_printf("OpenSBI: setting timer at %#lx\n", next_event);
+    set_aclint_mtimecmp0lo(aclint, (uint32_t)0xFFFFFFFF);
+    set_aclint_mtimecmp0hi(aclint, (uint32_t)(next_event >> 32));
+    set_aclint_mtimecmp0lo(aclint, (uint32_t)(next_event & 0xFFFFFFFF));
+}
+static void riscv_vp_timer_event_stop(void){
+    // sbi_printf("OpenSBI: Cancelling pending event\n");
+    set_aclint_mtimecmp0lo(aclint, (uint32_t)0xFFFFFFFF);
+    set_aclint_mtimecmp0hi(aclint, (uint32_t)0xFFFFFFFF);
+}
+static int riscv_vp_timer_warm_init(void){
+    riscv_vp_timer_event_stop();
+    return 0;
+}
+static struct sbi_timer_device timer_device = {
+    .name = "riscv_vp_timer",
+    .timer_freq = 32768,  
+    .timer_value = riscv_vp_timer_value,
+    .timer_event_start = riscv_vp_timer_event_start,
+    .timer_event_stop = riscv_vp_timer_event_stop,
+    .warm_init = riscv_vp_timer_warm_init
+};
+
+static int platform_early_init(bool cold_boot){
+    if (cold_boot){
+        sbi_console_set_device(&minres_console);
+    }
+    return 0;
+}
+static int platform_final_init(bool cold_boot){       
+    if (cold_boot){
+        sbi_system_reset_add_device(&reset_device);
+        sbi_timer_set_device(&timer_device);
+    }
+    return 0;
+}
+
+static int platform_irqchip_init(void){
+	return 0;
+}
+
+static int platform_ipi_init(void){
+	return 0;
+}
+
+static int platform_timer_init(void){
+	return 0;
+}
+
+
+const struct sbi_platform_operations platform_ops = {
+    .early_init	= platform_early_init,
+    .final_init = platform_final_init,
+    .irqchip_init = platform_irqchip_init,
+	.ipi_init = platform_ipi_init,
+    .timer_init = platform_timer_init
+};
+
+
+const struct sbi_platform platform = {
+	.opensbi_version	= OPENSBI_VERSION,
+	.platform_version	= SBI_PLATFORM_VERSION(0x1, 0x07),
+	.name			= "riscv_vp",
+	.features		= SBI_PLATFORM_DEFAULT_FEATURES,
+	.hart_count		= 1,
+	.hart_stack_size	= SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
+	.heap_size		= SBI_PLATFORM_DEFAULT_HEAP_SIZE(1),
+	.platform_ops_addr	= (unsigned long)&platform_ops
+};

scripts/create-binary-archive.sh

@@ -102,6 +102,7 @@ build_opensbi() {
 		BUILD_PLATFORM_SUBDIR+=("nuclei/ux600")
 		BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
 		BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
+		BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
 		BUILD_PLATFORM_SUBDIR+=("generic")
 		;;
 	*)