Yu Chien Peter Lin
ef9f02e7fb
lib: utils/timer: Add Andes fdt timer support
...
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.
dts example (Quad-core AX45MP):
cpus {
...
timebase-frequency = <0x3938700>;
...
}
soc {
...
plmt0@e6000000 {
compatible = "andestech,plmt0";
reg = <0x00 0xe6000000 0x00 0x100000>;
interrupts-extended = <&cpu0_intc 0x07
&cpu1_intc 0x07
&cpu2_intc 0x07
&cpu3_intc 0x07>;
};
...
}
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
2022-10-23 10:26:39 +05:30
Anup Patel
eccb9df5cf
platform: Remove redundant config.mk from all platforms
...
The options defined in config.mk can be specified in objects.mk of each
platform so let us remove config.mk from all platforms.
Signed-off-by: Anup Patel <apatel@ventanamicro.com >
Tested-by: Andrew Jones <ajones@ventanamicro.com >
Acked-by: Atish Patra <atishp@rivosinc.com >
Tested-by: Atish Patra <atishp@rivosinc.com >
2022-08-08 09:34:25 +05:30
Nylon Chen
32f87e5a86
platform: Add AE350 cache control SBIs
...
This patch contains the following AE350 specific SBIs:
- get mcache_ctl status
- get mmisc_ctl status
- set mcache_ctl status
- set mmisc_ctl status
- I-cache operation
- D-cache operation
- enable/disable L1-I-cache prefetch
- enable/disable L1-D-cache prefetch
- enable/disable non-blocking load store
- enable/disable write-around
Signed-off-by: Nylon Chen <nylon7@andestech.com >
Reviewed-by: Anup Patel <Anup.Patel@wdc.com >
Reviewed-by: Atish Patra <Atish.Patra@wdc.com >
2020-06-10 09:28:52 +05:30
Bin Meng
6e87507db6
platform: ae350: Sort build objects in alphabetical order
...
Signed-off-by: Bin Meng <bmeng.cn@gmail.com >
Reviewed-by: Anup Patel <anup.patel@wdc.com >
2020-03-10 10:13:02 +05:30
Nylon Chen
3cbb419def
platform: Add Andes AE350 initial support
...
This commit provides basic support for the AE350 platform.
Signed-off-by: Zong Li <zongbox@gmail.com >
Signed-off-by: Nylon Chen <nylon7@andestech.com >
2019-08-23 16:25:56 +05:30
